Patent US1407133A successfully refreshed from Google Patents.
Patent US5890199A successfully refreshed from Google Patents.
US5890199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory
Assignee: Ramtron International Corp
•
Filing: 1996-10-21
•
Granted: 1999-03-30
•
Expires: 2016-10-21
Abstract
Abstract A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory mapper for receiving logical addresses from an arithmetic logic unit ("ALU") and converting the same to physical addresses within the memory array in accordance with configuration instructions stored in a local non-volatile memory. By utilizing a common memory technology for the memory array, such as non-volatile ferroelectric random access memory ("FRAM"), the proportions and layout of the memory array which may be utilized for MPU instructions and data may be selectably controlled. The use of a memory mapper also allows for the establishment of an effective password or encryption protection function for the memory array data of particular utility in conjunction with radio frequency identification ("RF/ID") transponders and other applications which must store sensitive data in non-volatile storage.
Inventors
- 👤 Jeffery E. Downs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G06F12/1408; G06F12/1458; G06F12/1466; G06F12/1475
Claims Analysis
Total Claims: 73
Claim 1
Independent Claim
61 words
An integrated circuit data processor comprising: an arithmetic logic unit in said integrated circuit; a memory array in said integrated circuit and addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus.
Claim 2
Dependent Claim
61 words
An integrated circuit data processor comprising: an arithmetic logic unit in said integrated circuit; a memory array in said integrated circuit and addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus.
Claim 3
Dependent Claim
20 words
The data processor of claim 1 wherein said read/write portion is capable of storing data for said arithmetic logic unit.
Claim 4
Dependent Claim
16 words
The data processor of claim 1 wherein said read/write portion comprises at least one write-protected portion.
Claim 5
Dependent Claim
23 words
The data processor of claim 1 wherein said read only portion is capable of storing instructions for operation of said arithmetic logic unit.
Claim 6
Dependent Claim
22 words
The data processor of claim 1 wherein said arithmetic logic unit and said memory array are monolithically integrated on a common substrate.
Claim 7
Dependent Claim
15 words
The data processor of claim 1 wherein said memory array comprises a non-volatile memory array.
Claim 8
Dependent Claim
17 words
The data processor of claim 6 wherein said non-volatile memory array comprises a ferroelectric random access memory.
Claim 9
Dependent Claim
24 words
The data processor of claim 7 wherein said ferroelectric random access memory comprises a number of capacitive elements having a lead zirconate titanate dielectric.
Claim 10
Dependent Claim
24 words
The data processor of claim 7 wherein said ferroelectric random access memory comprises a number of capacitive elements having a strontium bismuth tantalate dielectric.
Claim 11
Dependent Claim
43 words
The data processor of claim 1 further comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array.
Claim 12
Dependent Claim
34 words
The data processor of claim 10 wherein said memory mapper further comprises: a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 13
Dependent Claim
111 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable; and a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array.
Claim 14
Dependent Claim
111 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable; and a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array.
Claim 15
Dependent Claim
14 words
The data processor of claim 10 wherein said non-volatile memory is a ferroelectric memory.
Claim 16
Dependent Claim
66 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus, configuration data for said data processor being storable in said memory array.
Claim 17
Dependent Claim
66 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus, configuration data for said data processor being storable in said memory array.
Claim 18
Dependent Claim
22 words
The data processor of claim 14 wherein said configuration data is placed on said data bus upon reset of said data processor.
Claim 19
Dependent Claim
114 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus; and a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 20
Dependent Claim
114 words
A data processor including an arithmetic logic unit, said data processor comprising: a memory array addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus; and a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 21
Dependent Claim
95 words
An integrated data processor comprising: an arithmetic logic unit; a memory array accessible by said arithmetic logic unit for storing data therein; a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory array being addressable by said arithmetic logic unit and selectively configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit means.
Claim 22
Dependent Claim
95 words
An integrated data processor comprising: an arithmetic logic unit; a memory array accessible by said arithmetic logic unit for storing data therein; a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory array being addressable by said arithmetic logic unit and selectively configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit means.
Claim 23
Dependent Claim
84 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array; and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 24
Dependent Claim
84 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array; and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 25
Dependent Claim
50 words
The data processor of claim 17 wherein said memory array is addressable by said arithmetic logic unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus.
Claim 26
Dependent Claim
24 words
The data processor of claim 19 wherein said read/write portion of said memory array is capable of storing data for said arithmetic logic unit.
Claim 27
Dependent Claim
16 words
The data processor of claim 19 wherein said read/write portion comprises at least one write-protected portion.
Claim 28
Dependent Claim
27 words
The data processor of claim 19 wherein said read only portion of said memory array is capable of storing instructions for operation of said arithmetic logic unit.
Claim 29
Dependent Claim
22 words
The data processor of claim 17 wherein said arithmetic logic unit and said memory mapper are monolithically integrated on a common substrate.
Claim 30
Dependent Claim
15 words
The data processor of claim 17 wherein said memory array comprises a non-volatile memory array.
Claim 31
Dependent Claim
17 words
The data processor of claim 24 wherein said non-volatile memory array comprises a ferroelectric random access memory.
Claim 32
Dependent Claim
24 words
The data processor of claim 25 wherein said ferroelectric random access memory comprises a number of capacitive elements having a lead zirconate titanate dielectric.
Claim 33
Dependent Claim
24 words
The data processor of claim 25 wherein said ferroelectric random access memory comprises a number of capacitive elements having a strontium bismuth tantalate dielectric.
Claim 34
Dependent Claim
73 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, configuration data for said data processor being storable in said memory array.
Claim 35
Dependent Claim
73 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, configuration data for said data processor being storable in said memory array.
Claim 36
Dependent Claim
22 words
The data processor of claim 28 wherein said configuration data is placed on said data bus upon reset of said data processor.
Claim 37
Dependent Claim
85 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 38
Dependent Claim
85 words
A data processor including an arithmetic logic unit and a memory array accessible by said arithmetic logic unit for storing data therein, said data processor comprising: a memory mapper coupling said arithmetic logic unit and said memory array, said memory mapper for receiving a logical address from said arithmetic logic unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 39
Dependent Claim
80 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus.
Claim 40
Dependent Claim
80 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus.
Claim 41
Dependent Claim
15 words
The integrated circuit of claim 31 wherein said memory array comprises a non-volatile memory array.
Claim 42
Dependent Claim
17 words
The integrated circuit of claim 32 wherein said non-volatile memory array comprises a ferroelectric random access memory.
Claim 43
Dependent Claim
24 words
The integrated circuit of claim 33 wherein said ferroelectric random access memory comprises a number of capacitive elements having a lead zirconate titanate dielectric.
Claim 44
Dependent Claim
24 words
The integrated circuit of claim 33 wherein said ferroelectric random access memory comprises a number of capacitive elements having a strontium bismuth tantalate dielectric.
Claim 45
Dependent Claim
25 words
The integrated circuit of claim 31 wherein said address source comprises an arithmetic logic unit monolithically integrated with said memory mapper and said memory array.
Claim 46
Dependent Claim
34 words
The integrated circuit of claim 31 wherein said memory mapper further comprises: a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 47
Dependent Claim
124 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable: and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 48
Dependent Claim
124 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable: and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 49
Dependent Claim
14 words
The integrated circuit of claim 37 wherein said non-volatile memory is a ferroelectric memory.
Claim 50
Dependent Claim
104 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical addresses to said physical addresses.
Claim 51
Dependent Claim
104 words
An integrated circuit comprising: a memory mapper having an input bus for receiving logical addresses from an address source coupled thereto and an output bus for supplying physical addresses thereon corresponding to said logical addresses; and a memory array coupled to said output bus, said memory array being selectably configurable as at least one of a read/write portion and a read only portion thereof for supplying data to a data bus corresponding to said physical addresses on said output bus, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical addresses to said physical addresses.
Claim 52
Dependent Claim
97 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit disposed within said transponder through a bidirectional bus for reading data therefrom and writing data thereto, said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus.
Claim 53
Dependent Claim
97 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit disposed within said transponder through a bidirectional bus for reading data therefrom and writing data thereto, said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus.
Claim 54
Dependent Claim
23 words
The transponder of claim 41 wherein said read/write portion of said memory array is capable of storing data for said central processing unit.
Claim 55
Dependent Claim
15 words
The transponder of claim 41 wherein said read/write portion comprises at least one write-protected portion.
Claim 56
Dependent Claim
26 words
The transponder of claim 41 wherein said read only portion of said memory array is capable of storing instructions for operation of said central processing unit.
Claim 57
Dependent Claim
24 words
The transponder of claim 41 wherein said central processing unit, said RF modem and said memory array are monolithically integrated on a common substrate.
Claim 58
Dependent Claim
14 words
The transponder of claim 41 wherein said memory array comprises a non-volatile memory array.
Claim 59
Dependent Claim
16 words
The transponder of claim 46 wherein said non-volatile memory array comprises a ferroelectric random access memory.
Claim 60
Dependent Claim
23 words
The transponder of claim 47 wherein said ferroelectric random access memory comprises a number of capacitive elements having a lead zirconate titanate dielectric.
Claim 61
Dependent Claim
23 words
The transponder of claim 47 wherein said ferroelectric random access memory comprises a number of capacitive elements having a strontium bismuth tantalate dielectric.
Claim 62
Dependent Claim
42 words
The transponder of claim 41 further comprising: a memory mapper coupling said central processing unit and said memory array, said memory mapper for receiving a logical address from said central processing unit and supplying a corresponding physical address to said memory array.
Claim 63
Dependent Claim
33 words
The transponder of claim 50 wherein said memory mapper further comprises: a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 64
Dependent Claim
172 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto; said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable; a memory mapper coupling said central processing unit and said memory array, said memory mapper for receiving a logical address from said central processing unit and supplying a corresponding physical address to said memory array; and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 65
Dependent Claim
172 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto; said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus, said at least one read/write portion and said at least one read only portion of said memory array being dynamically programmable; a memory mapper coupling said central processing unit and said memory array, said memory mapper for receiving a logical address from said central processing unit and supplying a corresponding physical address to said memory array; and a non-volatile memory for receiving and storing data indicative of said logical address to said physical address correspondence for said memory mapper.
Claim 66
Dependent Claim
13 words
The transponder of claim 51 wherein said non-volatile memory is a ferroelectric memory.
Claim 67
Dependent Claim
106 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto; said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus, configuration data for said central processing unit being storable in said memory array.
Claim 68
Dependent Claim
106 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto; said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus, configuration data for said central processing unit being storable in said memory array.
Claim 69
Dependent Claim
22 words
The transponder of claim 54 wherein said configuration data is placed on said data bus upon reset of said central processing unit.
Claim 70
Dependent Claim
152 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto: said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus; a memory mapper coupling said central processing unit and said memory array, said memory mapper for receiving a logical address from said central processing unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 71
Dependent Claim
152 words
An RF/ID transponder including an antenna coupled to an RF data modem for receiving and transmitting data between said transponder and an associated RF controller, said RF data modem being coupled to a central processing unit through a bidirectional bus for reading data therefrom and writing data thereto: said transponder comprising: a memory array addressable by said central processing unit and selectably configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said central processing unit by means of said bidirectional bus; a memory mapper coupling said central processing unit and said memory array, said memory mapper for receiving a logical address from said central processing unit and supplying a corresponding physical address to said memory array, said memory mapper being configured to provide encryption for data in said memory array by translation of said logical address to said physical address.
Claim 72
Dependent Claim
52 words
A data processor comprising: an arithmetic logic unit; a memory array addressable by said arithmetic logic unit and selectably and dynamically configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus.
Claim 73
Dependent Claim
52 words
A data processor comprising: an arithmetic logic unit; a memory array addressable by said arithmetic logic unit and selectably and dynamically configurable as at least one of a read/write portion and a read only portion thereof for at least supplying data to said arithmetic logic unit by means of a data bus.
References Cited (Backward Citations)
US5109521A
Cited
US5237699A
Cited
US5426744A
Cited
US5521417A
Cited
US5204840A
Cited
US5253197A
Cited
US5426746A
Cited
US5495593A
Cited
US5515540A
Cited
US5255244A
Cited
US5361343A
Cited
US5438844A
Cited
US5491662A
Cited
US5721868A
Cited
US5394367A
Cited
US5774392A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |