Method and apparatus for serially programming an on-chip EPROM in a microcontroller

Claim 2

A microcontroller architecture for serially programming the microcontrollers on-chip EPROM, the microcontroller architecture comprising a) mode decode means responsive to a plurality of operating mode input signals for generating corresponding operating mode signals, including an EPROM mode signal; b) a clock generator for generating a load clock signal; c) an upper byte address shift register for serially receiving a most significant address portion of an EPROM address in response to a pphi clock input signal and for providing the most significant address portion as an upper byte parallel output; d) a lower byte address shift register for serially receiving a least significant address portion of an EPROM address in response to the pphi clock input signal and for providing the least significant address portion as a lower byte parallel output; e) a memory address register that loads the upper and lower byte parallel outputs from the upper and lower byte address shift registers, respectively, and provides an EPROM address as an output, the EPROM address including the most and least significant address portions, in response to an EPROM load signal; and f) an EPROM memory element comprising a plurality of storage elements and decoder means responsive to the EPROM address provided by the memory address register for providing access to a storage element specified by the EPROM address.

Claim 3

A microcontroller as in claim 1 and further including a data out register that receives a parallel output of the contents of the storage register specified by the EPROM address in response to a read clock signal and provides the contents as a serial output signal to a data out pin in response in the phi clock signal.

Claim 4

A microcontroller as in claim 2 and further including a data in register that receives a serial input signal from a data in pin in response to the pphi clock and loads its contents in parallel to the storage location specified by the EPROM address in response to a write signal and NRESET=VPP.

Claim 5

A microcontroller as in claim 1 and further including; a) an upper byte multiplexer that selects one of a plurality of upper byte address input signals as the most significant address portion in response to a corresponding select input signal, the address input signals including an externally-supplied upper byte signal, the externally-supplied upper byte signal being the selected upper address input signal when the select signal is the EPROM mode signal; b) a lower byte multiplexer that selects one of a plurality of lower address input signals as the least significant address portion in response to a corresponding select input signal, the lower address input signals including an externally-supplied lower byte signal, the externally-supplied lower byte signal being the selected lower address input signal when the select input signal is the EPROM mode signal; c) a clock multiplexer that selects one of a plurality of clock input signals as the shift clock signal in response to a corresponding select input signal, the clock input signals including an externally-supplied EPROM clock signal, the EPROM clock signal being the selected clock signal when the select signal is the EPROM mode signal; and d) a load clock multiplexer that selects one of a plurality of load clock signals as the pload clock signal in response to a corresponding select input signal, the load clock signals including an externally-supplied EPROM load clock signal, the EPROM load clock signal being the selected load clock signal when the select signal is the EPROM mode signal.

Claim 6

A microcontroller as in claim 1 and further comprising programming control logic responsive to a read input signal for enabling the contents of the storage location specified by the EPROM address to be read from the storage location and responsive to a write input signal for enabling the contents of the storage register specified by the EPROM address to be written.