Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate

Abstract

Abstract A method is provided for forming a non-volatile memory cell in which the upper surface of the floating gate is polished to reduce surface irregularities, providing for the formation of a gate dielectric having a relatively high breakdown voltage thereon. According to an embodiment, a first gate dielectric is thermally grown upon a semiconductor substrate which later serves as the tunnel dielectric in the ensuing memory cell. A floating gate polysilicon is deposited across the first gate dielectric, followed by ion implantation of dopants and nitrogen therein. The upper surface of the floating gate polysilicon is then polished using, e.g., CMP. A second gate dielectric comprising high quality oxynitride may then be thermally grown across the polished surface of the floating gate polysilicon. Alternately, a ceramic having a relatively high dielectric constant may be formed across the floating gate polysilicon to serve as the second gate dielectric. A control gate polysilicon may be formed across the second gate dielectric. After doping the control gate polysilicon, portions of the layers formed above the substrate may be removed to define sidewall surfaces of a stacked structure. Source and drain regions which are self-aligned to the sidewall surfaces of the stacked structure may then be formed within the substrate.

Inventors

• 👤 Mark I. Gardner
• 👤 Mark C. Gilmer

Bibliographic Details