US5654219A
Expired / Lapsed
US
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Annealed poly-silicide etch process
Assignee: Texas Instruments Inc
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Filing: 1996-02-07
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Granted: 1997-08-05
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Expires: 2016-02-07
Abstract
Abstract A method for forming poly-silicide conductors (CG,GAP) on a semiconductor device (10) includes forming a layer (14) of doped polysilicon over a region of the device (10), then depositing a layer (15) of refractory metal on the layer (14) of doped polysilicon. The layer (14) of doped polysilicon and the layer (15) of refractory metal are then annealed to form a poly-silicide layer (PSL). The poly-silicide layer (PSL) is then etched to form the poly-silicide conductors (CG,GAP).
Inventors
- 👤 Michael L. Huber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:36
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/44; H10B41/48; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
83 words
A method for narrowing the threshold voltage distribution of a nonvolatile memory cell array, the method comprising: forming a layer of doped polysilicon over a region of the device; depositing a layer of refractory metal silicide on the layer of doped polysilicon; annealing the layer of doped polysilicon and the layer of refractory metal silicide to form a poly-silicide layer; and etching the poly-silicide layer and the doped polysilicon layer to form control gates for the memory cells of said nonvolatile memory array.
Claim 2
Independent Claim
83 words
A method for narrowing the threshold voltage distribution of a nonvolatile memory cell array, the method comprising: forming a layer of doped polysilicon over a region of the device; depositing a layer of refractory metal silicide on the layer of doped polysilicon; annealing the layer of doped polysilicon and the layer of refractory metal silicide to form a poly-silicide layer; and etching the poly-silicide layer and the doped polysilicon layer to form control gates for the memory cells of said nonvolatile memory array.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein said refractory metal silicide is tungsten silicide.
Claim 4
Dependent Claim
50 words
The method of claim 1, wherein the step of depositing said refractory metal silicide layer comprises deposition of a layer about 1000 Angstroms thick with a silicon-tungsten ratio of 2.4 to 1 followed by deposition of a layer about 1500 Angstroms thick with a silicon-tungsten ratio of 2.6 to 1.
Claim 5
Dependent Claim
38 words
The method of claim 1, wherein the step of annealing comprises subjecting the device to a temperature of about 900° C. for about 10 minutes in a nitrogen ambient at a flow rate of 18 liters per minute.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |