Method for minimizing warp in the production of electronic assemblies

Claim 1

A laminated substrate adapted for mounting a semiconductor device comprising: a plurality of dielectric and conductive layers including a core layer, said plurality of dielectric layers, conductive layers and core layer arranged in alternatingly disposed, vertically stacked dielectric and conductive layers about a plane of symmetry passing through the core layer, wherein the conductive layers and the core layer are made of copper and the dielectric layers are comprised at least in part of an expanded polytetrafluoroethylene (ePTFE), wherein the dielectric layers include first and second dielectric layers disposed respectively on opposite sides of the core layer, and the first and second dielectric layers are made of the same material, and have approximately the same thickness and the same thickness tolerance, wherein outer-most layers of the stack are conductive layers having substantially the same thickness, and the thickness of the outer-most conductive layers are thicker than any other conductive layers except for the core layer, wherein an amount of said dielectric layers have a higher elastic modulus relative to said other dielectric layers, wherein at least some of said dielectric layers having said higher elastic modulus are arranged outwardly, from said horizontal plane of symmetry, relative to said other dielectric layers such that the flexural modulus of said laminated substrate is substantially maximized.