Method for forming compact memory cell using vertical devices

Claim 1

A method for forming a memory cell in a semiconductor device, said method comprising the steps of: simultaneously forming a columnar portion of silicon material and a perpendicular portion of silicon material extending therefrom from a continuous section of a silicon substrate; implanting conductive dopants into a surface of said silicon material to form a first diffusion region in an upper surface of said columnar portion and a second diffusion region in a surface of said perpendicular portion about a base of said columnar portion; forming a conductive spacer about said columnar portion which is insulated from said columnar portion and said second diffusion region by a dielectric layer; forming an insulative layer about said first and second diffusion regions and conductive spacer, said insulative layer having a cavity therein to expose a major portion of said first diffusion region; forming a first capacitor electrode making contact to said first diffusion region, said first capacitor electrode being a cylindrical-shaped container electrode; forming a capacitor dielectric over said first capacitor electrode; and forming a second capacitor electrode over said capacitor dielectric.

Claim 2

A method for forming a memory cell in a semiconductor device, said method comprising the steps of: simultaneously forming a columnar portion of silicon material and a perpendicular portion of silicon material extending therefrom from a continuous section of a silicon substrate; implanting conductive dopants into a surface of said silicon material to form a first diffusion region in an upper surface of said columnar portion and a second diffusion region in a surface of said perpendicular portion about a base of said columnar portion; forming a conductive spacer about said columnar portion which is insulated from said columnar portion and said second diffusion region by a dielectric layer; forming an insulative layer about said first and second diffusion regions and conductive spacer, said insulative layer having a cavity therein to expose a major portion of said first diffusion region; forming a first capacitor electrode making contact to said first diffusion region, said first capacitor electrode being a cylindrical-shaped container electrode; forming a capacitor dielectric over said first capacitor electrode; and forming a second capacitor electrode over said capacitor dielectric.

Claim 4

A method for forming a memory cell in a semiconductor device, said method comprising the steps of: simultaneously forming a columnar portion of silicon material and a perpendicular portion of silicon material extending therefrom from a continuous section of a silicon substrate; forming an access transistor having its gate electrode surrounding said columnar portion of silicon material, a first source/drain electrode in an upper portion of said columnar portion and a second source/drain electrode in said perpendicular portion of silicon material that extends outwardly from a base of said columnar portion; and forming a storage capacitor having its storage electrode connecting to said first source/drain electrode, said storage electrode being a cylindrical-shaped container electrode.

Claim 5

A method for forming a memory cell in a semiconductor device, said method comprising the steps of: simultaneously forming a columnar portion of silicon material and a perpendicular portion of silicon material extending therefrom from a continuous section of a silicon substrate; forming an access transistor having its gate electrode surrounding said columnar portion of silicon material, a first source/drain electrode in an upper portion of said columnar portion and a second source/drain electrode in said perpendicular portion of silicon material that extends outwardly from a base of said columnar portion; and forming a storage capacitor having its storage electrode connecting to said first source/drain electrode, said storage electrode being a cylindrical-shaped container electrode.