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US5884061A
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Apparatus to perform source operand dependency analysis perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single processor cycle
Assignee: International Business Machines Corp
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Filing: 1995-05-01
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Granted: 1999-03-16
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Expires: 2015-05-01
Abstract
Abstract An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.
Inventors
- 👤 James Henry Hesson
- 👤 Jay LeBlanc
- 👤 Stephen J. Ciavaglia
- 👤 Walter Thomas Esling
- 👤 Pamela Anne Wilcox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:56
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3824; G06F9/3834; G06F9/3838; G06F9/384; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
138 words
A method of performing register renaming and rapid pipeline recovery in a pipelined microprocessor capable of issuing and executing instructions out-of-order in a single processor cycle comprising the steps of; temporarily storing program data and instructions to be executed; performing source operand dependency analysis; assigning rename tags to source operands which are yet to be calculated by prior instructions and supplying retiring tagged data in place of matching previously tagged source operands; providing instruction scheduling wherein oldest executable instructions are executed first by a plurality of execution units; dispatching executable instructions to a plurality of execution units and supplying the execution units with operands from the stored program data and previously tagged data; enabling any execution or memory access instruction to execute out-of-order; and temporarily storing operand results including tagged data to be retired from the execution units.
Claim 2
Independent Claim
138 words
A method of performing register renaming and rapid pipeline recovery in a pipelined microprocessor capable of issuing and executing instructions out-of-order in a single processor cycle comprising the steps of; temporarily storing program data and instructions to be executed; performing source operand dependency analysis; assigning rename tags to source operands which are yet to be calculated by prior instructions and supplying retiring tagged data in place of matching previously tagged source operands; providing instruction scheduling wherein oldest executable instructions are executed first by a plurality of execution units; dispatching executable instructions to a plurality of execution units and supplying the execution units with operands from the stored program data and previously tagged data; enabling any execution or memory access instruction to execute out-of-order; and temporarily storing operand results including tagged data to be retired from the execution units.
Claim 3
Dependent Claim
44 words
The method of performing register renaming and rapid pipeline recovery according to claim 1 wherein the step of assigning rename tags further comprises: allocating rename tags from a list of rename tags in circular order; and storing the rename tags in the rotating stack.
Claim 4
Dependent Claim
49 words
The method of performing register renaming and rapid pipeline recovery according to claim 2 wherein the step of temporarily storing program data and instructions further comprises: identifying one previously stored instruction as an oldest unexecuted instruction; and marking all instructions older than said oldest unexecuted instruction as being flushed.
Claim 5
Dependent Claim
28 words
The method of performing register renaming and rapid pipeline recovery according to claim 2 wherein the step of providing rapid pipeline recovery comprises partially flushing the rotating stack.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |