Patent US5884027A successfully refreshed from Google Patents.
US5884027A
Expired / Lapsed
US
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Architecture for an I/O processor that integrates a PCI to PCI bridge
Assignee: Intel Corp
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Filing: 1997-06-05
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Granted: 1999-03-16
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Expires: 2017-06-05
Abstract
Abstract A multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge. The invention consolidates a high performance processor, a PCI to PCI bus bridge, PCI bus-processor address translation unit, direct memory acces's (DMA) controller, memory controller, secondary PCI bus arbitration unit, inter-integrated circuit (I 2 C) bus interface unit, advanced programmable interrupt (APIC) bus interface unit, and a messaging unit into a single system which utilizes a local memory. The PCI bus is an industry standard high performance, low latency system bus. The PCI to PCI bridge provides a connection path between two independent 32-bit PCI buses and provides the ability to overcome PCI electrical loading limits. The addition of the local processor brings intelligence to the PCI bus bridge.
Inventors
- 👤 Elliot Garbus
- 👤 Peter Sankhagowit
- 👤 Marc Goldschmidt
- 👤 Nick Eskandari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
164 words
An integrated circuit for coupling a first PCI external bus to a second PCI external bus comprising: a) a first internal bus for coupling to said first PCI external bus; b) a second internal bus for coupling to said second PCI external bus; c) a PCI-PCI bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said first and second external PCI buses; d) a local processor having a local address space, said local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface; e) a local bus for passing data between said processor and a memory accessible within said local address space, f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.
Claim 2
Dependent Claim
164 words
An integrated circuit for coupling a first PCI external bus to a second PCI external bus comprising: a) a first internal bus for coupling to said first PCI external bus; b) a second internal bus for coupling to said second PCI external bus; c) a PCI-PCI bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said first and second external PCI buses; d) a local processor having a local address space, said local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface; e) a local bus for passing data between said processor and a memory accessible within said local address space, f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.
Claim 3
Dependent Claim
119 words
The integrated circuit defined by claim 1 further comprising: a) a first address translation circuit coupled to said local bus and said first internal bus adapted to convert for inbound transactions, addresses on said first internal bus to addresses usable by said local processor, and for outbound transactions, addresses on said local bus to addresses usable by devices coupled to said first external bus; b) a second address translation circuit coupled to said local bus and said second internal bus adapted to convert, for inbound transactions, addresses on said second internal bus to addresses usable by said local processor, and, for outbound transactions, addresses on said local bus to addresses usable by devices coupled to said second external bus.
Claim 4
Dependent Claim
77 words
The integrated circuit defined by claim 2 further comprising: a messaging circuit coupled to said first address translation circuit adapted to generate an interrupt for use by said local processor when new data is placed onto said first internal bus and to generate an interrupt on at least one interrupt line of said first internal bus when said local processor puts data onto said local bus for use by a device coupled to said first external bus.
Claim 5
Dependent Claim
57 words
The integrated circuit defined by claim 2 further comprising: a) a first bus arbitrator for controlling accesses to said first internal bus between said first bus interface and said first address translation circuit; b) a second bus arbitrator for controlling accesses to said second internal bus between said second bus interface and said second address translation circuit.
Claim 6
Dependent Claim
35 words
The integrated circuit defined by claim 2 further comprising: a local bus arbitrator for controlling accesses to said local bus among said local processor, said first address translation circuit and said second address translation circuit.
Claim 7
Dependent Claim
65 words
The integrated circuit defined by claim 1 further comprising: a first DMA controller coupled to said local bus and said first internal bus for transferring blocks of data between said first internal bus and said local memory; a second DMA controller coupled to said local bus and said second internal bus for transferring blocks of data between said second internal bus and said local memory.
Claim 8
Dependent Claim
66 words
The integrated circuit defined by claim 6 further comprising: a) a first bus arbitrator for controlling accesses to said first internal bus among said first bus interface, said first address translation circuit and said first DMA controller means; b) a second bus arbitrator for controlling accesses to said second internal bus among said second bus interface, said second address translation circuit and said second DMA controller.
Claim 9
Dependent Claim
48 words
The integrated circuit defined by claim 1 further comprising: a) a peripheral interrupt controller for routing a plurality of interrupt sources into a single interrupt input to said local processor means; b) a status register defining which one of said plurality of interrupt sources caused said single interrupt.
Claim 10
Dependent Claim
58 words
The integrated circuit defined by claim 1 further comprising: a) an I 2 C bus for coupling to external sensors suitable for management of a system utilizing said integrated circuit; b) an I 2 C interface for allowing said local processor means to serve as a master and slave device residing on said an I 2 C bus.
Claim 11
Dependent Claim
33 words
The integrated circuit defined by claim 1 further comprising: a) an APIC bus for coupling to external processors; b) an APIC interface for enabling communications between said external processors and said local processor.
Claim 12
Dependent Claim
58 words
The integrated circuit defined by claim 1 wherein said PCI-PCI bus bridge further comprises: a) a downstream posting buffer coupled between said first bus interface and said second bus interface; b) an upstream posting buffer coupled between said first bus interface and said second bus interface; c) a set of configuration registers coupled to said first bus interface.
Claim 13
Dependent Claim
14 words
The integrated circuit defined by claim 1 wherein said local processor comprises a microprocessor.
Claim 14
Dependent Claim
15 words
The circuit defined by claim 1 wherein said memory is external to said integrated circuit.
Claim 15
Independent Claim
161 words
A system including at least one host processor coupled to a primary PCI bus and at least one peripheral device coupled to a secondary PCI bus comprising in a single integrated circuit: a) a first internal bus coupled to said primary PCI bus; b) a second internal bus coupled to said secondary PCI bus; c a bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said primary PCI bus and said secondary PCI bus; d local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface; e a local bus for passing data between said processor and a memory; f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.
Claim 16
Independent Claim
161 words
A system including at least one host processor coupled to a primary PCI bus and at least one peripheral device coupled to a secondary PCI bus comprising in a single integrated circuit: a) a first internal bus coupled to said primary PCI bus; b) a second internal bus coupled to said secondary PCI bus; c a bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said primary PCI bus and said secondary PCI bus; d local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface; e a local bus for passing data between said processor and a memory; f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.
Claim 17
Dependent Claim
122 words
The system defined by claim 14 wherein said integrated circuit further comprises: a) a first address translation circuit coupled to said local bus and said first internal bus adapted to convert for inbound transactions addresses on said first internal bus to addresses usable by said local processor, and for outbound transactions addresses on said local bus to addresses usable by devices coupled to said primary PCI bus; b) a second address translation circuit coupled to said local bus and said second internal bus adapted to convert for inbound transactions addresses on said second internal bus to addresses usable by said local processor, and for outbound transactions addresses on said local bus to addresses usable by devices coupled to said secondary PCI bus.
Claim 18
Dependent Claim
80 words
The system defined by claim 15 wherein said integrated circuit further comprises: a messaging circuit coupled to said first address translation circuit adapted to generate an interrupt for use by said local processor when new data is placed onto said first internal bus and to generate an interrupt on at least one interrupt line of said first internal bus when said local processor puts data onto said local bus for use by a device coupled to said primary PCI bus.
Claim 19
Dependent Claim
61 words
The system circuit defined by claim 15 wherein said integrated circuit further comprises: a) a first bus arbitrator for controlling accesses to said first internal bus between said first bus interface and said first address translation circuit; b) a second bus arbitrator for controlling accesses to said second internal bus between said second bus interface and said second address translation circuit.
Claim 20
Dependent Claim
37 words
The system defined by claim 15 wherein said integrated circuit further comprises: local bus arbitrator for controlling accesses to said local bus among said local processor, said first address translation circuit and said second address translation circuit.
Claim 21
Dependent Claim
68 words
The system defined by claim 14 wherein said integrated circuit further comprises: a first DMA controller coupled to said local bus and said first internal bus for transferring blocks of data between said first internal bus and said local memory; a second DMA controller coupled to said local bus and said second internal bus for transferring blocks of data between said second internal bus and said local, memory.
Claim 22
Dependent Claim
69 words
The system defined by claim 19 wherein said integrated circuit further comprises: a) a first bus arbitrator for controlling accesses to said first internal bus among said first bus interface, said first address translation circuit and said first DMA controller means; b) a second bus arbitrator for controlling accesses to said second internal bus among said second bus interface, said second address translation circuit and said second DMA controller.
Claim 23
Dependent Claim
50 words
The system defined by claim 14 wherein said integrated circuit further comprises: a) a peripheral interrupt controller for routing a plurality of interrupt sources into a single interrupt input to said local processor; b) a status register defining which one of said plurality of interrupt sources caused said single interrupt.
Claim 24
Dependent Claim
61 words
The system circuit defined by claim 14 wherein said integrated circuit further comprises: a) an I 2 C bus for coupling to external sensors suitable for management of a system utilizing said integrated circuit; b) an I 2 C interface for allowing said local processor to serve as a master and slave device residing on said an I 2 C bus.
Claim 25
Dependent Claim
36 words
The system defined by claim 14 wherein said integrated circuit further comprises: a) an APIC bus for coupling to external processors; b) an APIC interface for enabling communications between said external processors and said local processor.
Claim 26
Dependent Claim
56 words
The system defined by claim 14 wherein said bus bridge further comprises: a) a downstream posting buffer coupled between said first bus interface and said second bus interface; b) an upstream posting buffer coupled between said first bus interface and said second bus interface; c) a set of configuration registers coupled to said first bus interface.
Claim 27
Dependent Claim
13 words
The system defined by claim 14 wherein said local processor comprises a microprocessor.
Claim 28
Dependent Claim
15 words
The system defined by claim 14 wherein said memory is external to said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |