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US5877074A
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Method for improving the electrical property of gate in polycide structure
Assignee: United Microelectronics Corp
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Filing: 1997-12-29
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Granted: 1999-03-02
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Expires: 2017-12-29
Abstract
Abstract A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.
Inventors
- 👤 Pei-Ren Jeng
- 👤 Chun-Cho Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:37
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A method of improving the electrical quality of gate in polycide structure, comprising the steps of: (a) forming a gate oxide layer on a silicon substrate; (b) forming a polysilicon layer on the surface of said gate oxide; (c) forming a layer of undoped amorphous silicon on the surface of said polysilicon layer; (d) forming a tungsten silicide layer on the surface of said undoped amorphous silicon layer; (e) performing at least one photolithography process to define at least one gate electrode; and (f) annealing; (g) wherein no annealing is performed between steps (c) and (e), so as to prevent said amorphous silicon from turning into polysilicon.
Claim 2
Independent Claim
107 words
A method of improving the electrical quality of gate in polycide structure, comprising the steps of: (a) forming a gate oxide layer on a silicon substrate; (b) forming a polysilicon layer on the surface of said gate oxide; (c) forming a layer of undoped amorphous silicon on the surface of said polysilicon layer; (d) forming a tungsten silicide layer on the surface of said undoped amorphous silicon layer; (e) performing at least one photolithography process to define at least one gate electrode; and (f) annealing; (g) wherein no annealing is performed between steps (c) and (e), so as to prevent said amorphous silicon from turning into polysilicon.
Claim 3
Dependent Claim
16 words
The method according to claim 1, wherein said polysilicon is formed through in-situ deposition with doping.
Claim 4
Dependent Claim
42 words
The method according to claim 2, wherein said in-situ deposition with doping is at pressure ranging from 0.3 to 0.6 Torr and temperature ranging from 575° C. to 650° C., the thickness of said polysilicon is ranging from 1100 to 1300 Å.
Claim 5
Dependent Claim
14 words
The method according to claim 2, wherein said first doping is performed with phosphorus.
Claim 6
Dependent Claim
23 words
The method according to claim 4, wherein the concentration of said phosphorus is ranging from 1.0×10 19 to 1.0×10 22 /cm 3 .
Claim 7
Dependent Claim
44 words
The method according to claim 1, wherein said undoped amorphous silicon is deposited at pressure ranging from 0.3 to 0.6 Torr and temperature ranging from 500° C. to 600° C., the thickness of said undoped amorphous silicon is ranging from 200 to 400 Å.
Claim 8
Dependent Claim
19 words
The method according to claim 1, wherein said temperature of annealing is ranging from 800° C. to 950° C.
References Cited (Backward Citations)
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