Modular MOSFETS for high aspect ratio applications

Claim 1

A modular MOS device to implement high aspect ratio of channel width to channel length FET devices, wherein the channel width is many times larger than the channel length, said modular MOS device comprising: a plurality of modules on a common substrate, each of said plurality of modules comprising: a plurality of FETs, each of said FETs including a plurality of interdigitated finger gate structures of predetermined sizes between alternating source and drain structures, a FET source line commonly connecting the source structures to a first strap on a first level of metalization, a FET drain line commonly connecting the drain structures to a second strap on said first level of metalization, and a FET gate line commonly connecting each of said interdigitated finger gate structures to a third strap on said first level of metalization, each module being electrically isolated from other modules at said first level of metalization and a number of modules being determined by yield data and a designed channel width; a common source line, a common drain line and a common gate line on a third level of metalization and extending between said plurality of modules; and interconnect means comprising trim straps on a second level of metalization connecting said first, second and third strap of each module to said common source line, said common drain line, and said common gate line, respectively, said trim straps including selectively openable trim spots, any bad or unwanted devices in the modular structure being isolated by selectively opening said trim spots to provide a 100% yield of the FET devices and to define a channel width of the trimmed modular MOS device.