Power transistor having multifinger contacts

Claim 2

A power transistor comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane; the transistors having finger-shaped contacts, said finger-shaped contacts being arranged along a stripshaped contact surface to which a power feed is provided at only a first end of the strip-shaped contact surface; and spacings of successive contacts from said first end of said contact surface decreasing strictly monotonously to a second end of the contact surface.

Claim 3

The power transistor according to claim 1, wherein the individual transistors are arranged on a first surface of a semiconductor member and wherein a second surface of the semiconductor member lying opposite the first surface of the individual transistors is connected to a heat sink and remaining surfaces of the semiconductor member are at least approximately thermally insulated, and wherein the finger-shaped contacts are arranged such that a temperature distribution of the power transistor is substantially uniform, said temperature distribution being determined by a numerical solution of a static thermal conduction equation, ΔT (x, y, z) =0, by means of fast Fourier analysis, where an equation - K (T) ∇T (x, y, 0) = Q (x, y, 0) having a material-dependent and temperaturedependent thermal conduction coefficient K and at least one locusdependent heat source Q functions as boundary condition in the region of the contacts.

Claim 4

The power transistor according to claim 1, wherein a plurality of power transistors forms an array, and wherein the plurality of power transistors are integrated in common, provided with electrical terminals and arranged at such intervals relative to one another that a temperature distribution during operation of the array is substantially uniform.

Claim 5

A power transistor, comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane, each of said transistors having finger shaped contacts; at least one common strip-shaped contact along which said individual transistors are arranged, respective finger shaped contacts thereby defining a position of a respective individual transistor on said strip-shaped contact, spacings being provided between said individual transistors; at least some of said spacings being different in terms of size such that, during operation of the power transistor in a predetermined range of electrical nominal power, temperature distribution of the power transistor is substantially uniform.

Claim 6

A power transistor, comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane, each of said transistors having finger shaped contacts; at least one common strip-shaped contact along which said individual transistors are arranged, respective finger shaped contacts thereby defining a position of a respective individual transistor on said strip-shaped contact, spacings being provided between said individual transistors; at least some of said spacings being different in terms of size such that, during operation of the power transistor in a predetermined range of electrical nominal power, temperature distribution of the power transistor is substantially uniform.

Claim 7

The power transistor according to claim 4, wherein the individual transistors are arranged on a first surface of a semiconductor member and wherein a second surface of the semiconductor element lying opposite the individual transistors is connected to a heat sink and remaining surfaces of the semiconductor element are at least approximately thermally insulated, and wherein the finger-shaped contacts are arranged such that a temperature distribution of the power transistor is substantially uniform, said temperature distribution being determined by a numerical solution of a static thermal conduction equation, ΔT (x, y, z) = 0, by means of fast Fourier analysis, where an equation - K (T) ∇T (x, y, 0) = Q (x, y, 0) having a material-dependent and temperaturedependent thermal conduction coefficient K and at least one locusdependent heat source Q functions as boundary condition in the region of the contacts.

Claim 8

The power transistor according to claim 4, wherein finger-shaped contacts are arranged laterally along a stripshaped contact surface to which a power supply is connected at only one end thereof, and wherein spacings of successive contacts from the end of the contact surface connected to the power supply to the other end decrease strictly monotonously.

Claim 9

The power transistor according to claim 4, wherein finger-shaped contacts are arranged laterally along a strip-shaped contact surface to which a power supply is connected at both ends thereof, and wherein spacings of contacts following one another in a longitudinal direction of the contact surface vary relative to one another and are mirror-symmetrical relative to a straight line proceeding perpendicularly to the longitudinal direction of the strip-shaped contact surface through a middle thereof.

Claim 10

The power transistor according to claim 7, wherein the spacings of the finger-shaped contacts following one another in the longitudinal direction in a respective row are approximately identical with the exception of spacings present in a middle and at the ends, two middle contacts adjacent one another having a smaller spacing compared to spacing of the contacts extending in both directions from the two middle contacts, and respective contacts situated at the ends having a smaller spacing compared to respectively following contacts.

Claim 11

The power transistor according to claim 7, wherein a plurality of power transistors forms an array, and wherein the plurality of power transistors are integrated in common, provided with electrical terminals and arranged at such intervals relative to one another that a temperature distribution during operation of the array is substantially uniform.

Claim 12

A power transistor comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane on a first surface of a semiconductor member, each of said transistors having finger shaped contacts; at least one common strip-shaped contact along which said individual transistors are arranged, respective finger shaped contacts thereby defining a position of a respective individual transistor on said strip-shaped contact, spacings being provided between said individual transistors; at least some of said spacings being different in terms of size such that, during operation of the power transistor in a predetermined range of electrical nominal power, temperature distribution of the power transistor is substantially uniform; and a second surface of the semiconductor member lying opposite the first surface having the individual transistors connected to a heat sink and remaining surfaces of the semiconductor member being at least approximately thermally insulated, wherein the finger-shaped contacts are arranged such that a temperature distribution of the power transistor is substantially uniform, said temperature distribution of the power transistor is substantially uniform, said temperature distribution being determined by a numerical solution of a static thermal conduction equation, ΔT (x, y, z) = 0, by means of fast Fourier analysis, where an equation - K (T) ∇T (x, y, 0) = Q (x, y, 0) having a material-dependent and temperature-dependent thermal conduction coefficient K and at least one locus-dependent heat source Q functions as boundary condition in the region of the contacts.

Claim 13

A power transistor comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane on a first surface of a semiconductor member, each of said transistors having finger shaped contacts; at least one common strip-shaped contact along which said individual transistors are arranged, respective finger shaped contacts thereby defining a position of a respective individual transistor on said strip-shaped contact, spacings being provided between said individual transistors; at least some of said spacings being different in terms of size such that, during operation of the power transistor in a predetermined range of electrical nominal power, temperature distribution of the power transistor is substantially uniform; and a second surface of the semiconductor member lying opposite the first surface having the individual transistors connected to a heat sink and remaining surfaces of the semiconductor member being at least approximately thermally insulated, wherein the finger-shaped contacts are arranged such that a temperature distribution of the power transistor is substantially uniform, said temperature distribution of the power transistor is substantially uniform, said temperature distribution being determined by a numerical solution of a static thermal conduction equation, ΔT (x, y, z) = 0, by means of fast Fourier analysis, where an equation - K (T) ∇T (x, y, 0) = Q (x, y, 0) having a material-dependent and temperature-dependent thermal conduction coefficient K and at least one locus-dependent heat source Q functions as boundary condition in the region of the contacts.

Claim 14

The power transistor according to claim 10, wherein finger-shaped contacts are arranged laterally along a stripshaped contact surface to which a power supply is connected at only one end thereof, and wherein spacings of successive contacts from the end of the contact surface connected to the power supply to the other end decrease strictly monotonously.

Claim 15

The power transistor according to claim 10, wherein finger-shaped contacts are arranged laterally along a stripshaped contact surface to which a power supply is connected at both ends thereof, and wherein spacings of contacts following one another in a longitudinal direction of the contact surface vary relative to one another and are mirror-symmetrical relative to a straight line proceeding perpendicularly to the longitudinal direction of the strip-shaped contact surface through a middle thereof.

Claim 16

The power transistor according to claim 12, wherein spacings of the finger-shaped contacts following one another in the longitudinal direction in a respective row are approximately identical with the exception of spacings present in a middle and at the ends, two middle contacts adjacent one another having a smaller spacing compared to spacing of contacts following in both directions, and respective contacts situated at the ends having a smaller spacing compared to respectively following contacts.

Claim 17

The power transistor according to claim 12, wherein a plurality of power transistors forms an array, and wherein the plurality of power transistors are integrated in common, provided with electrical terminals and arranged at such intervals relative to one another that a temperature distribution during operation of the array is substantially uniform.

Claim 18

A power transistor comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane, the transistors having finger-shaped contacts; the finger-shaped contacts arranged laterally along a stripshaped contact surface to which a power supply is connected at both ends thereof; spacings of contacts following one another in a longitudinal direction of the contact surface varying relative to one another and mirror-symmetrical relative to a straight line proceeding perpendicularly to the longitudinal direction of the strip-shaped contact surface through a middle thereof; and the spacings of the finger-shaped contacts following one another in the longitudinal direction in a respective row being approximately identical with the exception of spacings present in a middle and at the ends, two middle contacts adjacent one another having a smaller spacing compared to spacing of contacts following in both directions, and respective contacts situated at the ends having a smaller spacing compared to respectively following contacts.

Claim 19

A power transistor comprising: a plurality of monolithically integrated, contacted individual transistors arranged in a single plane, the transistors having finger-shaped contacts; the finger-shaped contacts arranged laterally along a stripshaped contact surface to which a power supply is connected at both ends thereof; spacings of contacts following one another in a longitudinal direction of the contact surface varying relative to one another and mirror-symmetrical relative to a straight line proceeding perpendicularly to the longitudinal direction of the strip-shaped contact surface through a middle thereof; and the spacings of the finger-shaped contacts following one another in the longitudinal direction in a respective row being approximately identical with the exception of spacings present in a middle and at the ends, two middle contacts adjacent one another having a smaller spacing compared to spacing of contacts following in both directions, and respective contacts situated at the ends having a smaller spacing compared to respectively following contacts.

Claim 20

The power transistor according to claim 15, wherein the individual transistors are arranged on a first surface of a semiconductor member and wherein a second surface of the semiconductor member lying opposite the first surface of the individual transistors is connected to a heat sink and remaining surfaces of the semiconductor member are at least approximately thermally insulated, and wherein the finger-shaped contacts are arranged such that a temperature distribution of the power transistor is substantially uniform, said temperature distribution being determined by a numerical solution of a static theraml conduction equation, ΔT (x, y, 0) = 0, by means of fast Fourier analysis, where an equation - K (T) ∇T (x, y, 0) = Q (x, y, 0) having a material-dependent and temperature-dependent thermal conduction coefficient K and at least one locus-dependent heat source Q functions as boundary condition in the region of the contacts.

Claim 21

The power transistor according to claim 15, wherein a plurality of power transistors forms an array, and wherein the plurality of power transistors are integrated in common, provided with electrical terminals and arranged at such intervals relative to one another that a temperature distribution during operation of the array is substantially uniform.