US5872945A
Expired / Lapsed
US
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MX bus translation to new system bus protocol
Assignee: Intel Corp
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Filing: 1996-11-14
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Granted: 1999-02-16
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Expires: 2016-11-14
Abstract
Abstract A bus translator is provided to translate the internal bus structure of a self-contained processor system to a system bus which is easily compatible with a plurality of different external components. In particular, the bus translator translates the packetized multiplexed internal bus to a de-multiplexed bus. The translator further provides the ability to add wait states to the transactions in order to accommodate slower memories and devices coupled to the system bus. Furthermore, the translator accommodates bus burst logic by providing an auto-increment addressing capability. In addition, as the processor operates on 32-bit words and coupled devices may operate on a smaller word size, the bus translator of the present invention provides a byte enable register file for performing byte operations within the 32-bit word operations of the system. Finally, the bus translator also provides accurate parity generation and checking on a byte basis. An external boot feature for the self-contained processor system allows the reading of start-up configuration data from internal non-volatile memory or system memory. Furthermore, address mapping and chip enable control allow the user to access additional information from the non-volatile memory regardless of the boot mode chosen.
Inventors
- 👤 Thomas E. Wett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
100 words
An apparatus comprising: a processor coupled to a de-multiplexed system bus and a multiplexed local bus; a nonvolatile memory coupled to the local bus, the nonvolatile memory storing internal configuration data and microcode; an external system memory coupled to the system bus, the system memory storing external configuration data, wherein the processor receives a selected one of the internal and the external configuration data as boot configuration data in accordance with a state of an internal/external signal coupled to the nonvolatile memory, wherein the processor receives the microcode from the nonvolatile memory regardless of the state of the internal/external signal.
Claim 2
Independent Claim
100 words
An apparatus comprising: a processor coupled to a de-multiplexed system bus and a multiplexed local bus; a nonvolatile memory coupled to the local bus, the nonvolatile memory storing internal configuration data and microcode; an external system memory coupled to the system bus, the system memory storing external configuration data, wherein the processor receives a selected one of the internal and the external configuration data as boot configuration data in accordance with a state of an internal/external signal coupled to the nonvolatile memory, wherein the processor receives the microcode from the nonvolatile memory regardless of the state of the internal/external signal.
Claim 3
Dependent Claim
17 words
The apparatus of claim 1 wherein the processor and the nonvolatile memory form a self-contained processor system.
Claim 4
Dependent Claim
17 words
The apparatus of claim 2 wherein the self-contained processor system resides on a single printed circuit board.
Claim 5
Dependent Claim
14 words
The apparatus of claim 2 wherein the self-contained processor system is a multi-chip module.
Claim 6
Dependent Claim
67 words
The apparatus of claim 1 wherein the processor further comprises a bus translator for communicating information between the multiplexed local bus and the de-multiplexed system bus, wherein the local bus multiplexes address signals and data signals on a same plurality of bus lines, the system bus having a plurality of address lines separate from a plurality of data lines, the system bus coupled to an external device.
Claim 7
Dependent Claim
190 words
The apparatus of claim 5 wherein the bus translator further comprises: control logic for controlling data transfer between the local bus and the system bus; a data register file storing write data from the processor and providing the write data to the system bus for the external device, the data register file storing read data from the external device and providing the read data to the local bus for the processor, wherein the write data and the read data are communicated between the external device and the data register file using the system bus in accordance with a state of a ready signal communicated to the control logic from the external device; and an address latch to latch write address signals from the local bus such that a write address can be provided to the address lines for each word of write data communicated from the data register file to the external device using the plurality of data lines, wherein the control logic generates wait states when communicating data between the data register file and the external device if the ready signal indicates that the external device is not ready.
Claim 8
Dependent Claim
106 words
The apparatus of claim 5, wherein the bus translator further comprises: burst address logic, the burst address logic receiving an initial write address accompanying a burst of write data from the processor, wherein the burst address logic provides the initial write address using the plurality of address lines and a first word of the burst write data to the external device using the data lines, wherein for each subsequent word of the burst write data the burst address logic increments the initial write address to provide an incremented write address with each subsequent word of burst write data to the external device using the system bus.
Claim 9
Dependent Claim
145 words
The apparatus of claim 5 wherein the bus translator further comprises: a byte enable register file to latch byte enable signals from the local bus such that a write byte enable signal is provided to the system bus for each word of write data communicated from the data register file to the external device in accordance with a ready signal communicated from the external device, wherein the byte enable register file latches byte enable signals from the system bus such that a read byte enable signal is provided to the local bus for each word of read data communicated from the data register file to the processor, wherein the read byte enable signal indicates the valid bytes for each word of read data from the external device, wherein the write byte enable signal indicates valid bytes for each word of write data from the processor.
Claim 10
Dependent Claim
94 words
The apparatus of claim 5 wherein the bus translator further comprises: parity generation logic generating at least one parity bit for each byte of each word of write data communicated to the external device, wherein the parity generation logic computes a calculated parity for each byte of read data from the external device, and parity check logic wherein if the calculated parity does not match a read data parity provided by the external device for each byte of read data then the parity check logic generates a parity error signal to the external device.
Claim 11
Independent Claim
143 words
An apparatus comprising: a processor coupled to a de-multiplexed system bus and a multiplexed local bus, wherein the local bus multiplexes address signals and data signals on a same plurality of bus lines, the system bus having a plurality of address lines separate from a plurality of data lines; a local nonvolatile memory coupled to the local bus and an internal/external signal, the local nonvolatile memory storing internal configuration data and microcode, wherein the processor and the local nonvolatile memory form a self-contained processor system; a system memory coupled to the system bus, the system memory storing external configuration data, wherein the processor receives boot configuration data from one of the system memory and the nonvolatile memory in accordance with the state of the internal/external signal, wherein the processor selects microcode from the nonvolatile memory independently of the state of the internal/external signal.
Claim 12
Independent Claim
143 words
An apparatus comprising: a processor coupled to a de-multiplexed system bus and a multiplexed local bus, wherein the local bus multiplexes address signals and data signals on a same plurality of bus lines, the system bus having a plurality of address lines separate from a plurality of data lines; a local nonvolatile memory coupled to the local bus and an internal/external signal, the local nonvolatile memory storing internal configuration data and microcode, wherein the processor and the local nonvolatile memory form a self-contained processor system; a system memory coupled to the system bus, the system memory storing external configuration data, wherein the processor receives boot configuration data from one of the system memory and the nonvolatile memory in accordance with the state of the internal/external signal, wherein the processor selects microcode from the nonvolatile memory independently of the state of the internal/external signal.
Claim 13
Dependent Claim
17 words
The apparatus of claim 10 wherein the processor and the nonvolatile memory form a self-contained processor system.
Claim 14
Dependent Claim
17 words
The apparatus of claim 11 wherein the self-contained processor system resides on a single printed circuit board.
Claim 15
Dependent Claim
14 words
The apparatus of claim 11 wherein the self-contained processor system is a multi-chip module.
Claim 16
Dependent Claim
36 words
The apparatus of claim 11 wherein the self-contained processor system further comprises: a bus translator for communicating information between the multiplexed local bus and the de-multiplexed system bus, the system bus coupled to an external device.
Claim 17
Dependent Claim
190 words
The apparatus of claim 14 wherein the bus translator further comprises: control logic for controlling data transfer between the local bus and the system bus; a data register file storing write data from the processor and providing the write data to the system bus for the external device, the data register file storing read data from the external device and providing the read data to the local bus for the processor, wherein the write data and the read data are communicated between the external device and the data register file using the system bus in accordance with a state of a ready signal communicated to the control logic from the external device; and an address latch to latch write address signals from the local bus such that a write address can be provided to the address lines for each word of write data communicated from the data register file to the external device using the plurality of data lines, wherein the control logic generates wait states when communicating data between the data register file and the external device if the ready signal indicates that the external device is not ready.
Claim 18
Dependent Claim
106 words
The apparatus of claim 14 wherein the bus translator further comprises: burst address logic, the burst address logic receiving an initial write address accompanying a burst of write data from the processor, wherein the burst address logic provides the initial write address using the plurality of address lines and a first word of the burst write data to the external device using the data lines, wherein for each subsequent word of the burst write data the burst address logic increments the initial write address to provide an incremented write address with each subsequent word of burst write data to the external device using the system bus.
Claim 19
Dependent Claim
145 words
The apparatus of claim 14 wherein the bus translator further comprises: a byte enable register file to latch byte enable signals from the local bus such that a write byte enable signal is provided to the system bus for each word of write data communicated from the data register file to the external device in accordance with a ready signal communicated from the external device, wherein the byte enable register file latches byte enable signals from the system bus such that a read byte enable signal is provided to the local bus for each word of read data communicated from the data register file to the processor, wherein the read byte enable signal indicates the valid bytes for each word of read data from the external device, wherein the write byte enable signal indicates valid bytes for each word of write data from the processor.
Claim 20
Dependent Claim
97 words
The apparatus of claim 14 wherein the bus translator further comprises: parity generation logic generating at least one parity bit for each byte of each word of write data communicated from the processor to the external device, wherein the parity generation logic computes a calculated parity for each byte of read data from the external device, and parity check logic wherein if the calculated parity does not match a read data parity provided by the external device for each byte of read data then the parity check logic generates a parity error signal to the external device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |