SRAM with transparent address latch and unlatched chip enable

Claim 2

A single chip address latched SRAM device comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having a plurality of input address lines and a plurality of output lines and operative to latch row address and column address inputs addressing particular locations in said memory array, and an address latch enable (ALE) input line, said address latch means being functionally transparent when an ALE input signal of a first logic state is applied to said ALE input line, said address latch means being operative to latch said output lines when an ALE input signal of a second logic state is applied to said ALE input line; data input/output means having a plurality of data input/output lines and a control input, said data input/output means being operative to selectively couple said plurality of data input/output lines to said memory array, and responsive to a control signal applied to said control input to determine when data is to be input thereto or output therefrom; and control logic means having at least three unlatched chip input lines for respectively receiving an output enable signal (G), a chip enable signal (E) and a write enable signal (W), said control logic means being directly responsive to the three enable signals G, E and W, and operative to develop said control signal for controlling said data I/O means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines, and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E is of a first logic state, said memory array is selected, and when E is of a second logic state, said memory array is deselected.

Claim 3

A single chip latched SRAM device as recited in claim 1 and further comprising: row decoder means and column decoder means associated with respective ones of said input address lines and operative to individually address selected word storage sites within said memory array.

Claim 4

A single chip latched SRAM device as recited in claim 2 and further comprising: column input/output means associated with said column decoder means and said data input/output means and operative to couple an addressed memory site to said input/output lines.

Claim 5

A single chip latched SRAM device as recited in claims 1-3 wherein said device is packaged in a 28-pin dual in-line pin-out package.

Claim 6

In a microcontroller including a microprocessor and one or more memory devices for storing processing data, an improved random access memory means embodied in one or more single chip integrated circuit devices each comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having a plurality of input address lines and a plurality of output lines and operative to latch row address and column address inputs addressing particular locations in said memory array, and an address latch enable (ALE) input line, said address latch means being functionally transparent when an ALE input signal of a first logic state is applied to said ALE input line, said address latch means being operative to latch said output lines when an ALE input signal of a second logic state is applied to said ALE input line; data input/output means having a plurality of data input/output lines and a control input, said data input/output means being operative to selectively couple said plurality of data input/output lines to said memory array, and responsive to a control signal applied to said control input to determine when data is to be input thereto or output therefrom; and control logic means having at least three unlatched chip input lines for respectively receiving an output enable signal (G), a chip enable signal (E) and a write enable signal (W), said control logic means being directly responsive to the three enable signals G, E and W, and operative to develop said control signal for controlling said data I/O means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines, and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E is of a first logic state, said memory array is selected, and when E is of a second logic state, said memory array is deselected.

Claim 7

In a microcontroller including a microprocessor and one or more memory devices for storing processing data, an improved random access memory means embodied in one or more single chip integrated circuit devices each comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having a plurality of input address lines and a plurality of output lines and operative to latch row address and column address inputs addressing particular locations in said memory array, and an address latch enable (ALE) input line, said address latch means being functionally transparent when an ALE input signal of a first logic state is applied to said ALE input line, said address latch means being operative to latch said output lines when an ALE input signal of a second logic state is applied to said ALE input line; data input/output means having a plurality of data input/output lines and a control input, said data input/output means being operative to selectively couple said plurality of data input/output lines to said memory array, and responsive to a control signal applied to said control input to determine when data is to be input thereto or output therefrom; and control logic means having at least three unlatched chip input lines for respectively receiving an output enable signal (G), a chip enable signal (E) and a write enable signal (W), said control logic means being directly responsive to the three enable signals G, E and W, and operative to develop said control signal for controlling said data I/O means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines, and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E is of a first logic state, said memory array is selected, and when E is of a second logic state, said memory array is deselected.

Claim 8

In a microcontroller as recited in claim 5 and further comprising: row decoder means and column decoder means associated with respective ones of said input address lines and operative to individually address selected word storage sites within each said memory array.

Claim 9

In a microcontroller as recited in claim 6 and further comprising: column input/output means associated with said column decoder means and said data input/output means and operative to couple an addressed memory site to said input/output lines.

Claim 10

In a microcontroller as recited in claim 5, 6 or 7, wherein said integrated circuit devices are packaged in 28-pin dual in-line pin-out (DIP) packages.

Claim 11

In a microcontroller as recited in claim 8 and further including chip select decoder means driven by high order address signals generated by said microprocessor and operative to develop said chip enable signals.

Claim 12

In a microcontroller as recited in claim 8 wherein the chip enable signal inputs of all of said integrated circuit devices are connected in common.

Claim 13

A single chip latched SRAM device as recited in claim 1 and further comprising: input/output control means for sensing when an address is too large for said address latch means and in response disabling said control logic means.

Claim 14

A single chip latched SRAM device as recited in claim 5 and further comprising: input/output control means for sensing when an address is too large for said address latch means and in response disabling said control logic means.