Fault-tolerant computer system with hidden local memory refresh

Claim 2

A fault tolerant computer system for processing an instruction stream, comprising: a plurality of processor modules, each of said processor modules executing said instruction stream, each processor module having: a processor for executing said instructions; an independent clock for providing clock cycles for controlling execution of said instruction stream independently of said other processor modules; a local memory coupled to said processor so as to be accessible thereby, wherein said local memory is of the type storing data in a dynamic manner and requiring periodic refresh to maintain data integrity; and local memory refresh control means for controlling said local memory refreshes such that said refreshes only occur when said processor is not requesting access to said local memory.

Claim 3

A fault tolerant computer system as set out in claim 1, wherein said processor provides a warning signal prior to accessing said local memory and wherein said local memory refresh control means receives said warning signal and delays any pending local memory refreshes in response thereto.

Claim 4

A fault tolerant computer system as set out in claim 2, wherein each said processor module further comprises means for receiving a processor request, partially decoding said request, and issuing a second warning signal to said local memory refresh controller means in response thereto.

Claim 5

A fault tolerant computer system as set out in claim 3, wherein said local memory refresh controller means receives said second warning signal and delays any pending local memory refreshes by a predetermined time in response thereto.

Claim 6

A fault tolerant computer system as set out in claim 4, wherein said predetermined period of time is one clock cycle.

Claim 7

A fault tolerant computer system as set out in claim 4, wherein each of said processor modules further comprises means for receiving a processor local memory access request and further decoding said instruction to provide a third warning signal to said local memory refresh controller means.

Claim 8

A fault tolerant computer system as set out in claim 6, wherein said local memory refresh control means aborts any pending local memory refreshes in response to said third warning signal.

Claim 9

A fault tolerant computer system as set out in claim 1, wherein said local memory refresh control means comprises a timer receiving said clock cycles and periodically providing a local memory refresh signal and memory control means responsive to said memory refresh control signal for initiating a local memory refresh in response to said signal only if an impending local memory access by the processor is not detected.

Claim 10

A fault tolerant computer system as set out in claim 1, wherein each of said local memories is clocked synchronously with the respective processor with which it is configured within a processor module and wherein said fault tolerant computer system further comprises one or more external memories clocked asynchronously with said processor modules.

Claim 11

A refresh controller for use with a computer system having a processor, a dynamic memory accessed by said processor, said processor issuing access requests prior to accessing said dynamic memory, and wherein said dynamic memory is of the type requiring periodic refreshes to maintain the integrity of data stored therein, and a clock for providing clock cycles, comprising: a refresh timer receiving said clock cycles and issuing a refresh request signal at predetermined refresh intervals; access warning means for receiving a request from said processor and providing a warning signal in response thereto; and refresh timing control means, coupled to said refresh timer and warning means and receiving said refresh request signal and said warning signal, for initiating a dynamic memory refresh in response to said refresh request signal and for stalling said refresh for a predetermined number of clock cycles in response to said warning signal.

Claim 12

A refresh controller for use with a computer system having a processor, a dynamic memory accessed by said processor, said processor issuing access requests prior to accessing said dynamic memory, and wherein said dynamic memory is of the type requiring periodic refreshes to maintain the integrity of data stored therein, and a clock for providing clock cycles, comprising: a refresh timer receiving said clock cycles and issuing a refresh request signal at predetermined refresh intervals; access warning means for receiving a request from said processor and providing a warning signal in response thereto; and refresh timing control means, coupled to said refresh timer and warning means and receiving said refresh request signal and said warning signal, for initiating a dynamic memory refresh in response to said refresh request signal and for stalling said refresh for a predetermined number of clock cycles in response to said warning signal.

Claim 13

A refresh controller as set out in claim 10, further comprising means for receiving a processor access request, decoding said request, and issuing a second warning signal to said refresh timing control means.

Claim 14

A refresh controller as set out in claim 11, wherein said refresh timing control means receives said second warning signal and delays any pending refresh by a predetermined period of time in response thereto.

Claim 15

A refresh controller as set out in claim 12, wherein said predetermined period of time is one clock cycle.

Claim 16

A refresh controller as set out in claim 11, further comprising means for receiving said processor access request and further decoding said request to provide a third warning signal to said refresh timing control means.

Claim 17

A refresh controller as set out in claim 14, wherein said refresh timing control means aborts any pending memory refresh in response to said third warning signal.

Claim 20

A fault tolerant computer system for processing an instruction stream, comprising: first, second and third processors of substantially identical configuration, said first, second and third processors having independent clocks providing independent clock cycles, each of said processors periodically issuing a command; first, second and third local memories respectively clocked synchronously with said first, second and third processors and accessible thereby, wherein said first, second and third local memories are of the dynamic type requiring periodic refresh to maintain data integrity of data stored therein; wherein said first, second and third processors issue one of a plurality of commands, wherein execution of predetermined ones of the plurality of commands involves accessing at least one of said first, second and third local memories; and first, second and third local memory refresh control means for periodically initiating a speculative local memory refresh operation and for, in response to said issued processor command, stalling said speculative local memory refresh for a predetermined period of time.

Claim 21

A fault tolerant computer system for processing an instruction stream, comprising: first, second and third processors of substantially identical configuration, said first, second and third processors having independent clocks providing independent clock cycles, each of said processors periodically issuing a command; first, second and third local memories respectively clocked synchronously with said first, second and third processors and accessible thereby, wherein said first, second and third local memories are of the dynamic type requiring periodic refresh to maintain data integrity of data stored therein; wherein said first, second and third processors issue one of a plurality of commands, wherein execution of predetermined ones of the plurality of commands involves accessing at least one of said first, second and third local memories; and first, second and third local memory refresh control means for periodically initiating a speculative local memory refresh operation and for, in response to said issued processor command, stalling said speculative local memory refresh for a predetermined period of time.

Claim 22

A fault tolerant computer system as set out in claim 17, wherein said predetermined period of time is one clock cycle.

Claim 23

A fault tolerant computer system as set out in claim 17, wherein said first, second and third local memory refresh control means each further comprises means for decoding said processor command and in response to a decoded command indicting a local memory access, aborting said speculative refresh.