US5216635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for requesting access to a computer memory for refreshing
Assignee: NCR Voyix Corp
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Filing: 1991-07-24
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Granted: 1993-06-01
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Expires: 2011-07-24
Abstract
Abstract A system and method for requesting access to refresh a computer memory. Two lines are connected between a timer and arbiter. A memory refresh request signal is provided on the first line and is accorded a relatively low priority by the arbiter. If the first request is not granted within a predetermined period of time, a second memory refresh request signal is provided on the second line and is accorded a relatively high priority by the arbiter.
Inventors
- 👤 William J. Kass
- 👤 Michael R. Hilley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A system for requesting access to a computer memory for refreshing comprising: a timing circuit; an arbiter; and first and second lines connecting said circuit and arbiter for transferring first and second refresh request signals, respectively, from said circuit to said arbiter, said circuit includes a counter which receives a clock signal and periodically generates a request signal, and first and second flip-flops, each having a data input and output and a clock input; wherein the clock input of said first and second flip-flops are connected to said counter for receiving said request signal; wherein the data input of said first flip-flop is connected to a reference voltage source; and wherein the data input of said second flip-flop is connected to the output of said first flip-flop; wherein the output of said first flip-flop is connected to said first request line and the output of said second flip-flop is connected to said second request line.
Claim 2
Independent Claim
155 words
A system for requesting access to a computer memory for refreshing comprising: a timing circuit; an arbiter; and first and second lines connecting said circuit and arbiter for transferring first and second refresh request signals, respectively, from said circuit to said arbiter, said circuit includes a counter which receives a clock signal and periodically generates a request signal, and first and second flip-flops, each having a data input and output and a clock input; wherein the clock input of said first and second flip-flops are connected to said counter for receiving said request signal; wherein the data input of said first flip-flop is connected to a reference voltage source; and wherein the data input of said second flip-flop is connected to the output of said first flip-flop; wherein the output of said first flip-flop is connected to said first request line and the output of said second flip-flop is connected to said second request line.
Claim 3
Dependent Claim
19 words
The system of claim 1 wherein each of said flip-flops has a reset input connected to said third line.
Claim 4
Dependent Claim
25 words
The system of claim 2 wherein said circuit further includes: a delay element connected between said third line and the reset input of said flip-flops.
Claim 5
Dependent Claim
75 words
The system of claim 1 wherein said circuit further comprises: a third flip-flop having a data input and output and a clock input; wherein the clock input of said third flip-flop is connected to said counter for receiving said request signal; wherein the data input of said third flip-flop is connected to the output of said first flip-flop; and wherein the output of said third flip-flop provides a signal indicating multiple refresh operations are requested.
Claim 6
Dependent Claim
19 words
The system of claim 4 wherein each of said flip-flops has a reset input connected to said third line.
Claim 7
Dependent Claim
53 words
The system of claim 5 wherein said circuit further includes: first and second delay elements, said first element connected between said third line and the reset input of said first and second flip-flops, and said first and second elements serially connected between said third line and the reset input of said third flip-flop.
Claim 8
Independent Claim
234 words
A system for requesting access to a computer memory for refreshing comprising: a timing circuit; an arbiter; first and second lines connecting said circuit and arbiter for transferring first and second refresh request signals, respectively, from said circuit to said arbiter; a third line connecting said circuit and arbiter for transmitting an acknowledge signal from said arbiter to said circuit; and additional lines connected to said arbiter for transferring other memory access request signals to said arbiter; wherein said arbiter arbitrates between said refresh and other memory access request signals; and wherein said arbiter ascribes the highest priority to said second refresh request signal; said circuit includes a counter which receives a clock signal and periodically generates a request signal; first and second flip-flops, each having a data input, data output, clock input and reset input; and a first delay element connected between said third line and the reset input of said flip-flops; wherein the clock input of said first and second flip-flops are connected to said counter for receiving said request signal; wherein the data input of said first flip-flop is connected to a reference voltage source; wherein the data input of said second flip-flop is connected to the output of said first flip-flop; and wherein the output of said first flip-flop is connected to said first request line and the output of said second flip-flop is connected to said second request line.
Claim 9
Independent Claim
234 words
A system for requesting access to a computer memory for refreshing comprising: a timing circuit; an arbiter; first and second lines connecting said circuit and arbiter for transferring first and second refresh request signals, respectively, from said circuit to said arbiter; a third line connecting said circuit and arbiter for transmitting an acknowledge signal from said arbiter to said circuit; and additional lines connected to said arbiter for transferring other memory access request signals to said arbiter; wherein said arbiter arbitrates between said refresh and other memory access request signals; and wherein said arbiter ascribes the highest priority to said second refresh request signal; said circuit includes a counter which receives a clock signal and periodically generates a request signal; first and second flip-flops, each having a data input, data output, clock input and reset input; and a first delay element connected between said third line and the reset input of said flip-flops; wherein the clock input of said first and second flip-flops are connected to said counter for receiving said request signal; wherein the data input of said first flip-flop is connected to a reference voltage source; wherein the data input of said second flip-flop is connected to the output of said first flip-flop; and wherein the output of said first flip-flop is connected to said first request line and the output of said second flip-flop is connected to said second request line.
Claim 10
Dependent Claim
103 words
The system of claim 7 wherein said circuit further comprises: a third flip-flop having a data input, data output, clock input and reset input; and a second delay element; wherein said first and second delay elements are serially connected between said third line and the reset input of said third flip-flop; wherein the clock input of said third flip-flop is connected to said counter for receiving said request signal; wherein the data input of said third flip-flop is connected to the output of said first flip-flop; and wherein the output of said third flip-flop provides a signal indicating multiple refresh operations are requested.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |