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US5872903A
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Integrated circuit device with a memory that preserves its content independently of a synchronizing signal when given a self-control request
Assignee: Mitsubishi Electric Corp
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Filing: 1997-02-24
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Granted: 1999-02-16
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Expires: 2017-02-24
Abstract
Abstract When a CPU (1) writes "10" into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of "0" by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of "1" to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.
Inventors
- 👤 Shunichi Iwata
- 👤 Mitsugu Satou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:22
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0891; G06F15/00; G06F15/76; G06F15/78; G06F1/00; G06F1/26; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
91 words
An integrated circuit device, comprising: a synchronizing signal generation circuit which stops generation of a synchronizing signal when given a standby request; a processing circuit for executing an instruction while receiving said synchronizing signal; a memory circuit which performs an operation while receiving said synchronizing signal and preserves its content therein independently when given a self-control request; and a control circuit for performing a sequential supply of said self-control request and said standby request when a write signal having a value of a first logic is given by said processing circuit.
Claim 2
Dependent Claim
91 words
An integrated circuit device, comprising: a synchronizing signal generation circuit which stops generation of a synchronizing signal when given a standby request; a processing circuit for executing an instruction while receiving said synchronizing signal; a memory circuit which performs an operation while receiving said synchronizing signal and preserves its content therein independently when given a self-control request; and a control circuit for performing a sequential supply of said self-control request and said standby request when a write signal having a value of a first logic is given by said processing circuit.
Claim 3
Dependent Claim
16 words
The integrated circuit device of claim 1, further comprising: a register for storing said write signal.
Claim 4
Dependent Claim
50 words
The integrated circuit device of claim 1, further comprising a cache, wherein said control circuit conducts a purge of said cache before said sequential supply of said self-control request and said standby request when said write signal having said value of said first logic is given by said processing circuit.
Claim 5
Dependent Claim
27 words
The integrated circuit device of claim 3, wherein said control circuit shuts out any interrupt request to be given thereto in said purge and said sequential supply.
Claim 6
Dependent Claim
51 words
The integrated circuit device of claim 1, wherein said control circuit selectively cuts off said synchronizing signal to be inputted to said processing circuit by generating an enable signal with a logic indicating "non-permission" when said write signal having a value of a second logic is given by said processing circuit.
Claim 7
Dependent Claim
90 words
An integrated circuit device, comprising: a synchronizing signal generation circuit which stops generation of a synchronizing signal when given a standby request; a processing circuit for executing an instruction while receiving said synchronizing signal; a memory circuit which performs an operation while receiving said synchronizing signal and preserves its content therein when given a self-control request; and a control circuit for performing a sequential supply of said self-control request and said standby request when a write signal having a value of a first logic is given by said processing circuit.
Claim 8
Dependent Claim
90 words
An integrated circuit device, comprising: a synchronizing signal generation circuit which stops generation of a synchronizing signal when given a standby request; a processing circuit for executing an instruction while receiving said synchronizing signal; a memory circuit which performs an operation while receiving said synchronizing signal and preserves its content therein when given a self-control request; and a control circuit for performing a sequential supply of said self-control request and said standby request when a write signal having a value of a first logic is given by said processing circuit.
Claim 9
Dependent Claim
16 words
The integrated circuit device of claim 6, further comprising: a register for storing said write signal.
Claim 10
Dependent Claim
50 words
The integrated circuit device of claim 6, further comprising a cache, wherein said control circuit conducts a purge of said cache before said sequential supply of said self-control request and said standby request when said write signal having said value of said first logic is given by said processing circuit.
Claim 11
Dependent Claim
27 words
The integrated circuit device of claim 8, wherein said control circuit shuts out any interrupt request to be given thereto in said purge and said sequential supply.
Claim 12
Dependent Claim
51 words
The integrated circuit device of claim 6, wherein said control circuit selectively cuts off said synchronizing signal to be inputted to said processing circuit by generating an enable signal with a logic indicating "non-permission" when said write signal having a value of a second logic is given by said processing circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |