Method for manufacturing a vertical mosfet including a back gate electrode

Claim 3

The method of manufacturing a semiconductor device of claim 1, wherein said first source region and said first drain region are formed by introducing an impurity using said first gate electrode and said first back gate electrode as a mask in said step (e).

Claim 4

The method of manufacturing a semiconductor device of claim 1, wherein said conductors are polysilicon.

Claim 5

The method of manufacturing a semiconductor device of claim 1, further comprising the step of: preparing a substrate having an insulating surface in which said first semiconductor region is formed and with which said first drain region comes into contact, before said step (a).

Claim 6

The method of manufacturing a semiconductor device of claim 1, further comprising the step of: (f) forming a second semiconductor region including (f-1) a major surface; and (f-2) a pillar-like portion extending vertically from said major surface of said second semiconductor region, having (f-2-1) an outer surface perpendicular to said major surface of said second semiconductor region; and (f-2-2) an inner surface opposite to said outer surface of said second semiconductor region; (g) forming a second gate insulating film on said outer surface of said second semiconductor region, and forming a second back gate insulating film on said inner surface of said second semiconductor region; and (h) forming a second source region in an upper end portion of said pillar-like portion of said second semiconductor region, and forming a second drain region in said major surface of said second semiconductor region so as to have a portion overlapping said bottom surface of said second gate electrode with said second gate insulating film interposed therebetween, wherein said steps (f) and (g) are performed concurrently with said steps (a) and (b), respectively, said conductors are also formed on said second gate insulating film and said second back gate film in said step (c), further in said step (d), (d-3) a second gate electrode including (d-3-1) a side surface opposed to said outer surface of said second semiconductor region with said second gate insulating film interposed therebetween; and (d-3-2) a bottom surface opposed to said major surface of said second semiconductor region with said second gate insulating film interposed therebetween; and (d-4) a second back gate electrode opposed to said inner surface of said second semiconductor region with said second back gate insulating film interposed therebetween are formed, and a first thickness between said outer surface of said first semiconductor region and said inner surface of said first semiconductor region and a second thickness between said outer surface of said second semiconductor region and said inner surface of said semiconductor region are different from each other.

Claim 7

The method of manufacturing a semiconductor device of claim 1, wherein said step (e) includes the steps of (e-1) forming a low-concentration region having said portion overlapping said bottom surface of said first gate electrode; and (e-2) forming a high-concentration region so as to have a distance from said first back gate electrode longer than that of said low-concentration region and an impurity concentration higher than that of said low-concentration region, to enhance an impurity concentration of said first source region.

Claim 8

The method of manufacturing a semiconductor device of claim 6, wherein said step (e-2) has the steps of (e-2-1) forming a side wall along a second side surface opposite to said first side surface of said first gate electrode; and (e-2-2) introducing an impurity using said first gate electrode, said first back gate electrode and said side wall as a mask.