Patent US5867726A successfully refreshed from Google Patents.
US5867726A
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US
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Microcomputer
Assignee: Renesas Electronics Corp
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Filing: 1996-04-10
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Granted: 1999-02-02
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Expires: 2016-04-10
Abstract
Abstract A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
Inventors
- 👤 Hiroshi Ohsuga
- 👤 Atsushi Kiuchi
- 👤 Hironobu Hasegawa
- 👤 Toru Baji
- 👤 Koki Noguchi
- 👤 Yasushi Akao
- 👤 Shiro Baba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:33
CPC Classifications
G; G06; G06F; G06F12/00; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3893; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7817; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/3004; G06F9/30043; G06F9/30098; G06F9/3012; G06F9/3013; G06F9/30145; G06F9/30149; G06F9/3016; G06F9/30167; G06F9/3017; G06F9/34; G06F9/345; G06F9/355; G06F9/3552; G06F9/3802; G06F9/3814; G06F9/3824; G06F9/3877
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
193 words
A microcomputer formed into a semiconductor integrated circuit on a semiconductor chip, comprising: a central processing unit; first to third address buses to which an address is selectively transferred from the central processing unit; a first memory connected to the first address bus and the second address bus and accessed by an address transferred from the central processing unit; a second memory connected to the first address bus and the third address bus and accessed by an address transferred from the central processing unit; a first data bus connected to the first and second memories and the central processing unit to transfer data; a second data bus connected to the first memory to transfer data; a third data bus connected to the second memory to transfer data; an external interface circuit connected to the first address bus and the first data bus; a digital signal processing unit connected to the first to third data buses and synchronously operated by the central processing unit; and a control signal line for transferring a control signal for controlling operations of the digital signal processing unit from the central processing unit to the digital signal processing unit.
Claim 2
Dependent Claim
193 words
A microcomputer formed into a semiconductor integrated circuit on a semiconductor chip, comprising: a central processing unit; first to third address buses to which an address is selectively transferred from the central processing unit; a first memory connected to the first address bus and the second address bus and accessed by an address transferred from the central processing unit; a second memory connected to the first address bus and the third address bus and accessed by an address transferred from the central processing unit; a first data bus connected to the first and second memories and the central processing unit to transfer data; a second data bus connected to the first memory to transfer data; a third data bus connected to the second memory to transfer data; an external interface circuit connected to the first address bus and the first data bus; a digital signal processing unit connected to the first to third data buses and synchronously operated by the central processing unit; and a control signal line for transferring a control signal for controlling operations of the digital signal processing unit from the central processing unit to the digital signal processing unit.
Claim 3
Dependent Claim
21 words
A microcomputer according to claim 1, wherein the first memory and the second memory are a RAM and a ROM, respectively.
Claim 4
Dependent Claim
50 words
A microcomputer according to claim 2, wherein the central processing unit includes a modulo address output portion for outputting values in an address register to the second or third address bus and generating addresses from the start address to the end address by repeatedly updating values in the address register.
Claim 5
Dependent Claim
80 words
A microcomputer according to claim 1, wherein the digital signal processor includes: first to third data buffer means to be individually interfaced with the first to third data buses; a plurality of register means connectable to each data buffer means through an internal bus; a multiplier and an arithmetic and logic operation unit connected to the internal bus; and a decoder for decoding the control signal and controlling the data buffer means, multiplier, arithmetic and logic unit, and register means.
Claim 6
Dependent Claim
136 words
A data processor on a semiconductor chip, comprising: a central processing unit; first to third address buses connected to the central processing unit; a first memory connected to the first and second address buses; a second memory connected to the first and third address buses; a first data bus connected to the first and second memories and the central processing unit; a second data bus connected to the first memory; a third data bus connected to the second memory; an interface circuit connected to the first address bus and the first data bus; a digital signal processing unit connected to the first to third data buses; and a control signal line for transferring a control signal for controlling operations of the digital signal processing unit from the central processing unit to the digital signal processing unit.
Claim 7
Dependent Claim
136 words
A data processor on a semiconductor chip, comprising: a central processing unit; first to third address buses connected to the central processing unit; a first memory connected to the first and second address buses; a second memory connected to the first and third address buses; a first data bus connected to the first and second memories and the central processing unit; a second data bus connected to the first memory; a third data bus connected to the second memory; an interface circuit connected to the first address bus and the first data bus; a digital signal processing unit connected to the first to third data buses; and a control signal line for transferring a control signal for controlling operations of the digital signal processing unit from the central processing unit to the digital signal processing unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |