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US5867725A
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Concurrent multitasking in a uniprocessor
Assignee: International Business Machines Corp
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Filing: 1996-03-21
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Granted: 1999-02-02
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Expires: 2016-03-21
Abstract
Abstract A superscalar uniprocessor that performs concurrent multi-task processing is provided. The processor of the present invention maintains a complete set of program address, memory control and general data registers for each task executing concurrently within the microprocessor, allowing independent control of the program flows. Each set of registers are associated with only one task and are utilized by the memory control and execution units to execute the associated task. The processor includes an instruction fetcher and memory management unit that retrieves an instruction from memory for a given task, as directed by the task's address and control registers, and attaches a task tag to the retrieved instruction that identifies that task. The superscalar processor has a plurality of execution units that can execute a plurality of tasks simultaneously, and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution. The instruction's task tag identifying the task is then associated with any result data that results from the execution of the instruction. The addition of task tag information in the program flow and in the register file provides for process utilization of execution resources simultaneously with, and substantially independently from other processes, thereby substantially enhancing concurrent multitasking in the superscalar uniprocessor.
Inventors
- 👤 Patrick Wai-Wah Fung
- 👤 Sebastian Theodore Ventrone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:21
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3842; G06F9/3851; G06F9/3861; G06F9/46; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
159 words
A concurrent-multitasking processor comprising: a plurality of execution units that can execute a plurality of tasks simultaneously; an instruction fetcher that retrieves an instruction from memory for a given task and attaches a task tag to the retrieved instruction, wherein the attached task tag identifies the task that requested the retrieved instruction; two or more of sets of registers, each set of registers having a respective associated task and being utilized by the instruction fetcher and the plurality of execution units for executing only the associated task, wherein each set of registers maintains a task tag identifying its associated task; and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution; wherein, when an instruction is executing in an execution unit, the execution unit utilizes only registers within the set of registers maintaining a task tag equivalent to the task tag attached to the executing instruction.
Claim 2
Dependent Claim
159 words
A concurrent-multitasking processor comprising: a plurality of execution units that can execute a plurality of tasks simultaneously; an instruction fetcher that retrieves an instruction from memory for a given task and attaches a task tag to the retrieved instruction, wherein the attached task tag identifies the task that requested the retrieved instruction; two or more of sets of registers, each set of registers having a respective associated task and being utilized by the instruction fetcher and the plurality of execution units for executing only the associated task, wherein each set of registers maintains a task tag identifying its associated task; and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution; wherein, when an instruction is executing in an execution unit, the execution unit utilizes only registers within the set of registers maintaining a task tag equivalent to the task tag attached to the executing instruction.
Claim 3
Dependent Claim
19 words
A concurrent-multitasking processor according to claim 1, wherein at least one set of registers includes a program address register.
Claim 4
Dependent Claim
19 words
A concurrent-multitasking processor according to claim 1, wherein at least one set of registers includes a memory control register.
Claim 5
Dependent Claim
24 words
A concurrent-multitasking processor according to claim 1, wherein at least one set of registers includes at least one general purpose or floating point register.
Claim 6
Dependent Claim
17 words
A concurrent-multitasking processor according to claim 1, wherein the task tags are maintained in their associated registers.
Claim 7
Dependent Claim
17 words
A concurrent-multitasking processor according to claim 1, wherein the task tags are maintained in a look-up table.
Claim 8
Dependent Claim
45 words
A concurrent-multitasking processor according to claim 1, said plurality of execution units comprising a load/store unit that loads from and stores to only the set of registers maintaining a task tag equivalent to the task tag attached to an instruction executing in the load/store unit.
Claim 9
Dependent Claim
68 words
A concurrent-multitasking processor according to claim 1, further comprising an exception handling mechanism that, in response to a task causing an exception in the processor, halts the execution of only instructions having an attached task tag that identifies the task causing the exception, and saves as the current state only data contained in the set of registers maintaining a task tag that identifies the task causing the exception.
Claim 10
Dependent Claim
57 words
A concurrent-multitasking processor according to claim 1, further comprising a branch processing unit that, in response to a task taking a mispredicted branch, flushes only instructions having an attached task tag identifying the task taking the mispredicted branch, allowing one of said plurality of execution units freed by flushing said instructions to be assigned to other tasks.
Claim 11
Dependent Claim
47 words
A concurrent-multitasking processor according to claim 1, wherein the result of an instruction executing in one of said plurality of execution units is saved in a register belonging to the set of registers maintaining a task tag equivalent to the task tag attached to the executing instruction.
Claim 12
Independent Claim
69 words
A method of concurrent multitasking in a processor, the method comprising the steps of: in response to a request by a task executing in the processor, receiving one or more requested instructions; associating a task tag with a received instruction that indicates the task that requested the instruction; and associating the task tag associated with a received instruction with result data that results from execution of the received instruction.
Claim 13
Independent Claim
69 words
A method of concurrent multitasking in a processor, the method comprising the steps of: in response to a request by a task executing in the processor, receiving one or more requested instructions; associating a task tag with a received instruction that indicates the task that requested the instruction; and associating the task tag associated with a received instruction with result data that results from execution of the received instruction.
Claim 14
Dependent Claim
47 words
A method of concurrent multitasking in a processor according to claim 11, further comprising: when executing a received instruction that requires operand data, utilizing, as the operand data, result data having an associated task tag that is equivalent to the task tag associated with the executing instruction.
Claim 15
Dependent Claim
40 words
A method of concurrent multitasking in a processor according to claim 12, wherein only result data having an associated task tag that is equivalent to the task tag associated with the executing instruction may be utilized as the operand data.
Claim 16
Dependent Claim
51 words
A method of concurrent multitasking in a processor according to claim 11, wherein the received instruction is a load instruction and the result data is stored in a register within the set of registers having an associated task tag that is equivalent to the task tag associated with the load instruction.
Claim 17
Dependent Claim
43 words
A method of concurrent multitasking in a processor according to claim 11, further comprising, in response to the execution of a store instruction, storing only data having an associated task tag that is equivalent to the task tag associated with the store instruction.
Claim 18
Dependent Claim
58 words
A method of concurrent multitasking in a processor according to claim 11, further comprising, in response to a task causing an exception in the processor, halting only instructions having an associated task tag indicating the task causing the exception, and saving as the current state only data having an associated task tag indicating the task causing the exception.
Claim 19
Dependent Claim
54 words
A method of concurrent multitasking in a processor according to claim 11, further comprising, in response to a task taking a mispredicted branch, flushing only instructions having an associated task tag indicating the task taking the mispredicted branch, such that an execution unit freed by flushing said instructions can be assigned to other tasks.
Claim 20
Independent Claim
70 words
A system providing concurrent multitasking in a processor, comprising: means for in response to a request by a task executing in the processor, receiving one or more requested instructions; means for associating a task tag with a received instruction that indicates the task that requested the instruction; and means for associating the task tag associated with a received instruction with result data that results from execution of the received instruction.
Claim 21
Independent Claim
70 words
A system providing concurrent multitasking in a processor, comprising: means for in response to a request by a task executing in the processor, receiving one or more requested instructions; means for associating a task tag with a received instruction that indicates the task that requested the instruction; and means for associating the task tag associated with a received instruction with result data that results from execution of the received instruction.
Claim 22
Dependent Claim
49 words
A system providing concurrent multitasking in a processor according to claim 18, further comprising means for, when executing a received instruction that requires operand data, utilizing, as the operand data, result data having an associated task tag that is equivalent to the task tag associated with the executing instruction.
Claim 23
Dependent Claim
40 words
A system providing concurrent multitasking in a processor according to claim 19, wherein only result data having an associated task tag that is equivalent to the task tag associated with the executing instruction may be utilized as the operand data.
Claim 24
Dependent Claim
51 words
A system providing concurrent multitasking in a processor according to claim 18, wherein the received instruction is a load instruction and the result data is stored in a register within the set of registers having an associated task tag that is equivalent to the task tag associated with the load instruction.
Claim 25
Dependent Claim
46 words
A system providing concurrent multitasking in a processor according to claim 18, further comprising means, in response responsive to the execution of a store instruction, for storing only data having an associated task tag that is equivalent to the task tag associated with the store instruction.
Claim 26
Dependent Claim
59 words
A system providing concurrent multitasking in a processor according to claim 18, further comprising means, responsive to a task causing an exception in the processor, for halting only instructions having an associated task tag indicating the task causing the exception, and saving as the current state only data having an associated task tag indicating the task causing the exception.
Claim 27
Dependent Claim
57 words
A system providing concurrent multitasking in a processor according to claim 18, further comprising means in response responsive to a task taking a mispredicted branch, for flushing only instructions having an associated task tag indicating the task taking the mispredicted branch, such that an execution unit freed by flushing said instructions can be assigned to other tasks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |