Triple-bus FIFO buffers that can be chained together to increase buffer depth

Claim 2

An integrated circuit comprising: a first FIFO buffer; an input port that provides an interface for writing data from outside the integrated circuit, into the first FIFO buffer; a second FIFO buffer: an output port that provides an interface for reading data from the second FIFO buffer, out of the integrated circuit; and a bi-directional port that provides an interface for reading data from the first FIFO buffer, out of the integrated circuit and an interface for writing data from outside the integrated circuit, into the second FIFO buffer, wherein the bi-directional port has a first data width and the input port has a second data width that differs from the first data width, and wherein the first FIFO buffer and the input port together comprise: a memory having the first data width; an input register having a plurality of independently accessible storage sections wherein output terminals from all the storage sections collectively provide a first data signal having the first data width; an input bus; and control logic which controls latching of data values represented by a second data signal on the input bus, wherein for each data value latched from the input bus, the control logic selects one of the storage sections into which the data value is stored, and wherein a value represented by the first data signal is written to the memory after each storage section stores a value from the second data signal.

Claim 3

The integrated circuit of claim 1, wherein the control logic is configurable to select storage section of the input register in different orders, a first order providing the first data signal with a value that is a big endian order combination of values from the second data signal, a second order providing the first data signal with a value that is a little endian order combination of values from the second data signal.

Claim 4

The integrated circuit of claim 1, wherein the bi-directional port has a first data width, and the output port has a second data width that differs from the first data width.

Claim 5

An integrated circuit comprising: a first FIFO buffer, an input port that provides an interface for writing data from outside the integrated circuit, into the first FIFO buffer; a second FIFO buffer; an output port that provides an interface for reading data from the second FIFO buffer, out of the integrated circuit; and a bi-directional port that provides an interface for reading data from the first FIFO buffer, out of the integrated circuit and an interface for writing data from outside the integrated circuit into the second FIFO buffer, wherein: the bi-directional port has a first data width, and the output port has a second data width that differs from the first data width, and data written into the second FIFO buffer in one access through the bi-direction port is transferred out of the second FIFO buffer through multiple accesses of the output port.

Claim 6

An integrated circuit comprising: a first FIFO buffer, an input port that provides an interface for writing data from outside the integrated circuit, into the first FIFO buffer; a second FIFO buffer; an output port that provides an interface for reading data from the second FIFO buffer, out of the integrated circuit; and a bi-directional port that provides an interface for reading data from the first FIFO buffer, out of the integrated circuit and an interface for writing data from outside the integrated circuit into the second FIFO buffer, wherein: the bi-directional port has a first data width, and the output port has a second data width that differs from the first data width, and data written into the second FIFO buffer in one access through the bi-direction port is transferred out of the second FIFO buffer through multiple accesses of the output port.

Claim 7

The integrated circuit of claim 4, wherein the output port is configurable to match data transferred during a first of the multiple accesses with a first group of bits or a second group of bits in the data transferred in the single access through the bi-directional port.

Claim 8

A first-in first-out buffer comprising a first buffer unit and a second buffer unit, wherein each buffer unit comprises: a first memory having an output interface comprising: a first terminal for input of an enable signal; a second terminal for output of an output-ready signal; an output data bus; a data selection circuit coupled to the first memory and the output data bus, wherein the data selection circuit reads the first memory and changes a data signal to represent at least a portion of a value read from the first memory, the changes being synchronized with a clock signal for the output interface and occurring while both the enable signal and the output-ready signal are asserted; and output control logic which asserts the output-ready signal to indicate the data signal on the data bus is ready to be read; a second memory having an input interface comprising: a third terminal for input of an enable signal; a fourth terminal for output of an input-ready signal; an input data bus; and input control logic which asserts the input-ready signal to indicate the input interface is ready to latch data indicated by a data signal on the input data bus, wherein latching data is synchronized with a clock signal for the input interface that occurs while both the input-ready signal and the enable signal are asserted, and wherein: the first, second, third, and fourth terminals of the first buffer unit are respectively coupled to the fourth, third, first, and second terminals of the second buffer unit; the output data bus of the first buffer unit is coupled to the input data bus of the second buffer unit; and the output data bus of the second buffer unit is coupled to the input data bus of the first buffer unit.

Claim 9

A first-in first-out buffer comprising a first buffer unit and a second buffer unit, wherein each buffer unit comprises: a first memory having an output interface comprising: a first terminal for input of an enable signal; a second terminal for output of an output-ready signal; an output data bus; a data selection circuit coupled to the first memory and the output data bus, wherein the data selection circuit reads the first memory and changes a data signal to represent at least a portion of a value read from the first memory, the changes being synchronized with a clock signal for the output interface and occurring while both the enable signal and the output-ready signal are asserted; and output control logic which asserts the output-ready signal to indicate the data signal on the data bus is ready to be read; a second memory having an input interface comprising: a third terminal for input of an enable signal; a fourth terminal for output of an input-ready signal; an input data bus; and input control logic which asserts the input-ready signal to indicate the input interface is ready to latch data indicated by a data signal on the input data bus, wherein latching data is synchronized with a clock signal for the input interface that occurs while both the input-ready signal and the enable signal are asserted, and wherein: the first, second, third, and fourth terminals of the first buffer unit are respectively coupled to the fourth, third, first, and second terminals of the second buffer unit; the output data bus of the first buffer unit is coupled to the input data bus of the second buffer unit; and the output data bus of the second buffer unit is coupled to the input data bus of the first buffer unit.

Claim 10

The buffer circuit of claim 6, wherein each of the first and second buffer units further comprises an input/output interface for providing input data to the first memory and output data from the second memory.

Claim 11

The buffer of claim 6, wherein the output control logic in each of the first and second buffer units deasserts the output-ready signal in response to the data selection circuit being unable to change the data signal during a next cycle of the clock signal.

Claim 12

The buffer of claim 6, further comprising a clock circuit which provides the clock signals for the input and output interfaces of the first and second buffer units.

Claim 13

The buffer of claim 6, wherein the clock signals for the input and output interfaces of the first and second buffer units are all identical.

Claim 14

The buffer of claim 6, wherein the first buffer unit is formed on a first integrated circuit and second buffer unit is formed on a second integrated circuit.