FIFO memory with decreased fall-through delay

Claim 2

A first in, first out data memory comprising a plurality of shift register sections, sequentially arranged and coupled for cascade operation, each of said sections comprising a predetermined number of shift register stages; each section having a smaller number of stages than the one preceding it; input means coupled to each section for writing data thereto; output means coupled to the last of said sections for reading date from said data memory; means for shifting data written to any one of said stages sequentially through the stages to the last of the stages which does not presently contain data; and means for selectively writing data directly into the section nearest the output means which is not presently full of data for the purpose of decreasing fall-through delay time.

Claim 3

A first in, first out data memory comprising a plurality of shift register sections, sequentially arranged and coupled for cascade operation, each of said sections comprising a predetermined number of shift register stages; each section having a small number of register stages than the one preceding it; input means coupled to each section for writing data thereto; a bypass bus, selectively coupled to the input means of each section, through which data is introduced; output means, coupled to the last of said sections, for reading data from said data memory; first status means, associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means, associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means, coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means, coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 4

A first in, first out data memory comprising a plurality of shift register sections, sequentially arranged and coupled for cascade operation, each of said sections comprising a predetermined number of shift register stages; each section having a small number of register stages than the one preceding it; input means coupled to each section for writing data thereto; a bypass bus, selectively coupled to the input means of each section, through which data is introduced; output means, coupled to the last of said sections, for reading data from said data memory; first status means, associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means, associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means, coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means, coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 5

A first in, first out data memory as claimed in claim 2, further including first clock input means, coupled to said bypass bus, for controlling the rate at which data is introduced onto said bypass bus; and second clock input means, coupled to said output means, for controlling the rate at which data is read from said data memory.

Claim 6

A first in, first out data memory as claimed in claim 2, wherein the number of register stages in the last of said sections is governed by the relationship N.sub.1 =T.sub.fallthru /T.sub.drip and the number of register stages in preceding sections is governed by the relationship N.sub.j =(N.sub.1 + . . . N.sub.(j-1))×(T.sub.shift -T.sub.bubble -T.sub.drip)/ T.sub.drip to optimize said register section lengths so that a continuous input data stream will not have time delay gaps introduced therein upon reading said output means; where Tfallthru is the desired fall-through delay for the FIFO, Tdrip is the time for a datum to move form one register stage to the next consecutive stage, Tshift is the required input or output time, and Tbubble is the time for a data vacancy to move from one register stage to the full stage preceding it.

Claim 7

A first in, first out data memory as claimed in claim 2, wherein said memory is constructed as a solid-state integrated circuit.

Claim 8

A programmable first in, first out data memory comprising a first bidirectional port for transferring data into or out of said data memory; a second bidirectional port for transferring data into or out of said data memory; control means, coupled to the first and second directional ports, for selecting the direction of data transfer through the ports; a register block including a plurality of shift register sections coupled for cascade operation, an input, and an output, such that data introduced at the input of the register block is shifted sequentially through the shift register sections to the output; each of said sections comprising a predetermined number of shift register stages; each section having a smaller number of register stages than the one preceding it; an input bus for transferring data from the first or second bidirectional port to the input of said register block; and an output bus for transferring data from the output of the register block to the first or second bidirectional port.

Claim 9

A programmable first in, first out data memory comprising a first bidirectional port for transferring data into or out of said data memory; a second bidirectional port for transferring data into or out of said data memory; control means, coupled to the first and second directional ports, for selecting the direction of data transfer through the ports; a register block including a plurality of shift register sections coupled for cascade operation, an input, and an output, such that data introduced at the input of the register block is shifted sequentially through the shift register sections to the output; each of said sections comprising a predetermined number of shift register stages; each section having a smaller number of register stages than the one preceding it; an input bus for transferring data from the first or second bidirectional port to the input of said register block; and an output bus for transferring data from the output of the register block to the first or second bidirectional port.

Claim 10

A programmable first in, first out data memory as recited in claim 6, further comprising means for selectively writing data directly into the section nearest the output means which is not presently full of data for the purpose of decreasing fall-through delay time.

Claim 11

A first in, first out data memory circuit, as recited in claim 6, further including data error detection means coupled to at least one port.

Claim 12

A first in, first out data memory circuit, as recited in claim 6, further including data recirculating means coupled to at least one port.

Claim 13

A first in, first out data memory circuit as recited in claim 6, wherein said memory is constructed as a solid-state integrated circuit.