Register device for transmission of data having two data ranks one of which receives data only when the other is full

Claim 2

A ripple register device comprising: a primary data rank register having an output connected as the ripple register device data output, a secondary data rank register having a data output connected to an input of said primary data rank register, means for providing input data of the ripple register device as an input to said primary and secondary data rank registers, a first control means for providing a control signal to said primary and secondary data rank registers, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register if said primary data rank register is initially empty and said ripple register device receives input data in said secondary data rank register if said primary data rank register is full.

Claim 3

The device of claim 1 wherein said first control means is a flip-flop.

Claim 4

The device of claim 1 wherein said second control means is a flip-flop.

Claim 5

The device of claim 1 or 2 or 3 wherein said first control means produces an output Hold signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register contains data.

Claim 6

The device of claim 1 or 2 or 3 wherein said second control means produces an output Full signal for connection to a succeeding device in a transmission path when said primary data rank register contains data.

Claim 7

A data transmission system consisting of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said ripple register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports.

Claim 8

A data transmission system consisting of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said ripple register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports.

Claim 9

The transmission system of claim 6 wherein each ripple register device is comprised of: a primary data rank register having an output connected as the ripple register device data output, a secondary data rank register having a data output connected to an input of said primary data rank register, means for providing input data of the ripple register device as an input to said primary and secondary data rank registers, a first control means for providing a control signal to said primary and secondary data rank registers, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register if said primary data rank register is initially empty and said ripple register device receives input data in said secondary data rank register if said primary data rank register is full.

Claim 10

The device of claim 7 wherein said first control means is a flip-flop.

Claim 11

The device of claim 7 wherein said second control means is a flip-flop.

Claim 12

The device of claim 7 or 8 or 9 wherein said first control means produces an output Hold signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register contains data.

Claim 13

The device of claim 7 or 8 or 9 wherein said second control means produces an output Full signal for connection to a succeeding device in a transmission path when said primary data rank register contains data.

Claim 14

A ripple register device comprising: a clock signal source means for providing a single phase clock signal, a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means and having a clock signal input for controlling timing of data transfers, means for providing input data of the ripple register device as an input to said primary and secondary data rank registr means, a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, said first control means having a clock signal input for controlling timing of output signals of said ripple register device, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and a single phase clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, said clock control means being connected to said primary data rank register means and to said second control means, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full.

Claim 15

A ripple register device comprising: a clock signal source means for providing a single phase clock signal, a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means and having a clock signal input for controlling timing of data transfers, means for providing input data of the ripple register device as an input to said primary and secondary data rank registr means, a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, said first control means having a clock signal input for controlling timing of output signals of said ripple register device, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and a single phase clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, said clock control means being connected to said primary data rank register means and to said second control means, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full.

Claim 16

The device of claim 12 wherein said first control means is a flip-flop.

Claim 17

The device of claim 12 wherein said second control means is a flip-flop.

Claim 18

The device of claim 12 or 13 or 14 wherein said first control means produces a Hold "out" signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register means contains data.

Claim 19

The device of claim 12 or 13 or 14 wherein said second control means produces a Full "out" signal for connection to a succeeding device in a transmission path when said primary data rank register means contains data.

Claim 20

A data transmission system comprised of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports and wherein each ripple register device is comprised of: a clock signal source means for providing a single phase clock signal, a primary data rank register means having an output connected as the ripple register device data "out" port, a secondary data rank register means having a data output connected to an input of said primary data rank register means and having a clock signal input for controlling timing of data transfers, means for providing input data from said data "in" port as an input to said primary and secondary data rank register means, a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, said first control means having a clock signal input for controlling timing of output signals of said ripple register device, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and a single phase clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, said clock control means being connected to said primary data rank register means and to said second control means, wherein said ripple register device received input data in said primary data rank register means if said primary data rank register means is initially empty and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full.

Claim 21

A data transmission system comprised of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports and wherein each ripple register device is comprised of: a clock signal source means for providing a single phase clock signal, a primary data rank register means having an output connected as the ripple register device data "out" port, a secondary data rank register means having a data output connected to an input of said primary data rank register means and having a clock signal input for controlling timing of data transfers, means for providing input data from said data "in" port as an input to said primary and secondary data rank register means, a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, said first control means having a clock signal input for controlling timing of output signals of said ripple register device, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and a single phase clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, said clock control means being connected to said primary data rank register means and to said second control means, wherein said ripple register device received input data in said primary data rank register means if said primary data rank register means is initially empty and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full.

Claim 22

The device of claim 17 wherein said first control means is a flip-flop.

Claim 23

The device of claim 17 wherein said second control means is a flip-flop.

Claim 24

The device of claim 17 or 18 or 19 wherein the first control means produces a Hold "out" signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register means contains data.

Claim 25

The device of claim 17 or 18 or 19 wherein said second control means produces a Full "out" signal for connection to a succeeding device in a transmission path when said primary data rank register means contains data.

Claim 26

A ripple register device comprising: a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means, means for providing input data of the ripple register device as an input to said primary and secondary data rank register means a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty or if data is being transferred out of said primary data rank register means and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full and will remain full.

Claim 27

A ripple register device comprising: a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means, means for providing input data of the ripple register device as an input to said primary and secondary data rank register means a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty or if data is being transferred out of said primary data rank register means and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full and will remain full.

Claim 28

The device of claim 22 wherein said first control means is a flip-flop.

Claim 29

The device of claim 22 wherein said second control means is a flip-flop.

Claim 30

The device of claim 22 or 23 or 24 wherein said first control means produces an output Hold signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register means contains data.

Claim 31

The device of claim 22 or 23 or 24 wherein said second control means produces an output Full signal for connection to a succeeding device in a transmission path when said primary data rank register means contains data.

Claim 32

A data transmission system comprised of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports and wherein each ripple register device is comprised of: a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means, means for providing input data from said data "in" port as an input to said primary and secondary data rank register means a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty or if data is being transferred out of said primary data rank register means and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full and will remain full.

Claim 33

A data transmission system comprised of a plurality of identical ripple register devices adapted to be connected serially between a sending device and a receiving device in which each of said register devices has a data "in" port and a data "out" port, a Hold "in" port connected to a succeeding device and a Hold "out" port connected with a preceding device and a Full "out" port connected with a succeeding device and a Full "in" port connected with a preceding device wherein said Full "out" port transmits information that the particular ripple register device is prepared to transmit data and wherein said Hold "out" port transmits information that the particular ripple register device cannot receive data, wherein each particular ripple register device has at least two data registers so that data may be both received and transmitted simultaneously in response to independent signals at the Full "in" and Hold "in" ports and wherein each ripple register device is comprised of: a primary data rank register means having an output connected as the ripple register device data output, a secondary data rank register means having a data output connected to an input of said primary data rank register means, means for providing input data from said data "in" port as an input to said primary and secondary data rank register means a first control means for providing a control signal to said primary and secondary data rank register means, said first control means with a first control signal input for connection to a preceding device in a data transmission path and said first control means with a second control signal input for connection to a succeeding device in a transmission path, a second control means for providing a control signal output, said second control means with a first control signal input connected to an output of said first control means and said second control means with a second control signal input for connection to a preceding device in a transmission path, and clock control means, having at least a clock signal input, for controlling gating of data from said primary data rank register means to a succeeding device in a transmission path, wherein said ripple register device receives input data in said primary data rank register means if said primary data rank register means is initially empty or if data is being transferred out of said primary data rank register means and said ripple register device receives input data in said secondary data rank register means if said primary data rank register means is full and will remain full.

Claim 34

The device of claim 27 wherein said first control means is a flip-flop.

Claim 35

The device of claim 27 wherein said second control means is a flip-flop.

Claim 36

The device of claim 27 or 28 or 29 wherein said first control means produces a Hold "out" signal for connection to a preceding device in a transmission path to cause said preceding device to hold data when said secondary data rank register means contains data.

Claim 37

The device of claim 27 or 28 or 29 wherein said second control means produces a Full "out" signal for connection to a succeeding device in a transmission path when said primary data rank register means contains data.