Patent US3902827A successfully refreshed from Google Patents.
Patent US5866441A successfully refreshed from Google Patents.
US5866441A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Inverted chip bonded module with high packaging efficiency
Assignee: Network Protection Sciences LLC
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Filing: 1996-12-16
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Granted: 1999-02-02
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Expires: 2016-12-16
Abstract
Abstract An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of semiconductor devices. The input/output pads of the semiconductor devices are simultaneously bonded to the protuberances of the packaging module.
Inventors
- 👤 Benedict G. Pace
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:40
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/40; H05K3/4007; H10; H10W; H10W40/00; H10W40/70; H10W40/77; H10W40/778; H10W70/00; H10W70/01; H10W70/05; H10W70/092; H10W70/095; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/641; H10W70/66; H10W70/67; H10W70/69; H10W70/692; H10W70/698; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W90/00; H10W90/701; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/0364; H05K2201/0367; H05K3/46; H05K3/4644; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/20; H10W72/251; H10W72/252
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
345 words
A method of manufacturing a circuit module having a conductive pattern that interconnects input/output pads of at least one semiconductor device to a higher level electronic package, comprising: providing an insulating, planar, inorganic substrate selected from the group consisting of silicon, sapphire and ceramics and glass/ceramics comprising aluminum oxide, aluminum nitride, beryllium oxide, boron nitride, cordierite, mullite, silicon carbide and silicon nitride, the substrate having holes filled with conductive feed-throughs; forming a metallic, conductive pattern layer on at least one planar surface of the inorganic substrate, the conductive pattern layer making contact to the conductive feed-throughs; applying an inorganic, dielectric composition over the conductive pattern layer, the composition forming an inorganic insulating layer; forming openings in the insulating layer, the openings being formed where metallic connections to the conductive pattern layer are required; repeating the steps of forming a metallic conductive pattern and forming an inorganic insulating layer with openings for each of the conductive pattern layers that is required to complete the conductive pattern, each conductive pattern layer making interconnections to previous conductive pattern layers by filling the openings in the insulating layer applied to the previous conductive pattern layer; the openings in the inorganic insulating layer over an outermost conductive pattern layer being formed in positions selected to correspond to input/output pads of the semiconductor device(s) and to expose contact points on the conductive pattern layer; depositing a soft, ductile metal into the openings, the metal filling the opening, electrically connecting to the conductive pattern and forming metal protuberances over the filled openings, the protuberances rising at least 0.01 mm (0.4 mils) beyond the outer surface of the insulating layer, the deposited metal being capable of being metallurgically bonded to the input/output pads of the semiconductor device(s); placing at least one semiconductor device with the input/output pads of the device over the metal protuberances, and simultaneously bonding all the input/output pads of the semiconductor device to the metal protuberances, forming interconnections from the input/output pads of the semiconductor device, through the conductive pattern and the conductive feed-throughs to the higher level electronic package.
Claim 2
Independent Claim
345 words
A method of manufacturing a circuit module having a conductive pattern that interconnects input/output pads of at least one semiconductor device to a higher level electronic package, comprising: providing an insulating, planar, inorganic substrate selected from the group consisting of silicon, sapphire and ceramics and glass/ceramics comprising aluminum oxide, aluminum nitride, beryllium oxide, boron nitride, cordierite, mullite, silicon carbide and silicon nitride, the substrate having holes filled with conductive feed-throughs; forming a metallic, conductive pattern layer on at least one planar surface of the inorganic substrate, the conductive pattern layer making contact to the conductive feed-throughs; applying an inorganic, dielectric composition over the conductive pattern layer, the composition forming an inorganic insulating layer; forming openings in the insulating layer, the openings being formed where metallic connections to the conductive pattern layer are required; repeating the steps of forming a metallic conductive pattern and forming an inorganic insulating layer with openings for each of the conductive pattern layers that is required to complete the conductive pattern, each conductive pattern layer making interconnections to previous conductive pattern layers by filling the openings in the insulating layer applied to the previous conductive pattern layer; the openings in the inorganic insulating layer over an outermost conductive pattern layer being formed in positions selected to correspond to input/output pads of the semiconductor device(s) and to expose contact points on the conductive pattern layer; depositing a soft, ductile metal into the openings, the metal filling the opening, electrically connecting to the conductive pattern and forming metal protuberances over the filled openings, the protuberances rising at least 0.01 mm (0.4 mils) beyond the outer surface of the insulating layer, the deposited metal being capable of being metallurgically bonded to the input/output pads of the semiconductor device(s); placing at least one semiconductor device with the input/output pads of the device over the metal protuberances, and simultaneously bonding all the input/output pads of the semiconductor device to the metal protuberances, forming interconnections from the input/output pads of the semiconductor device, through the conductive pattern and the conductive feed-throughs to the higher level electronic package.
Claim 3
Dependent Claim
30 words
A method according to claim 1, wherein the metal of the metal protuberances is selected from the group comprising aluminum, gold, indium, lead, silver, tin and alloys of these metals.
Claim 4
Dependent Claim
15 words
A method according to claim 2, wherein the metal of the metal protuberances is gold.
Claim 5
Dependent Claim
14 words
A method according to claim 3, wherein the insulating layer(s) are fired, inorganic compositions.
Claim 6
Dependent Claim
18 words
A method according to claim 4, wherein the metal of the metallic, conductive pattern is gold or copper.
Claim 7
Dependent Claim
18 words
A method according to claim 5, wherein at least one conductive pattern layer comprises thick film metal conductors.
Claim 8
Dependent Claim
24 words
A method according to claim 6, wherein at least one conductive pattern layer comprises a conductors photolithographically etched from a thick film metal layer.
Claim 9
Dependent Claim
23 words
A method according to claim 7, wherein at least one conductive pattern layer comprises conductors photolithographically etched from a thin film metal layer.
Claim 10
Dependent Claim
20 words
A method according to claim 1, wherein the conductive pattern and the semiconductor device(s) are encapsulated by a plastic composition.
Claim 11
Dependent Claim
33 words
A method according to claim 2, wherein the conductive pattern and the semiconductor device(s) are enclosed by a frame, the frame being bonded to the ceramic substrate, the frame being metal or ceramic.
Claim 12
Dependent Claim
46 words
A method according to claim 10, wherein at least one metal plug is placed in contact with the base of at least one of the semiconductor device(s), the metal plug(s) being bonded to the frame, and being capable of conducting heat away from the semiconductor device(s).
Claim 13
Dependent Claim
143 words
A method according to claim 1, wherein the substrate is a standardized, ceramic substrate having cofired refractory metal feed-throughs, the feed-throughs being arranged in an area array on a standard pattern, and the standardized substrate being adapted for a custom design by: forming the metallic, conductive pattern layer on the surface of the substrate, the layer making contact only to feed-throughs required by the custom design; applying the dielectric composition and forming the inorganic insulating layer over the metallic, conductive pattern layer and over all feed-throughs not in contact with the conductive pattern layer; forming the openings in the insulating layer the openings contacting only the metallic, conductive layer and feed-throughs required to make connection to subsequent conductive pattern layers, and the remaining feed-throughs, not required for the custom design, being inactive and isolated from the conductive pattern by the inorganic insulating layer.
Claim 14
Dependent Claim
97 words
A method according to claim 1, wherein the substrate is a standardized, ceramic substrate having cofired refractory metal feed-throughs, the feed-throughs being arranged in an area array on a standard pattern, further comprising the standardized substrate being adapted for a custom design by: applying a dielectric composition and forming an inorganic insulating layer over the feed-throughs and forming openings exposing only the feed-throughs required for the conductive pattern prior to forming a metallic, conductive pattern layer, and isolating and inactivating the remaining feed-throughs not required for the custom design from the conductive pattern by the insulating layer.
Claim 15
Dependent Claim
106 words
In a method of manufacturing a rigid circuit module having a conductive pattern of one or more conductive pattern layers, the improvement comprising forming, on at least one surface of the module, soft, ductile metal protuberances capable of being metallurgically bonded to the input/output pads of at least one semiconductor device; the protuberances protruding above the surface of the module far enough to compensate for variations due to the camber, planarity and overall size of both the module and the semiconductor device, and the metal protuberances being connected to the conductive pattern and formed in an array corresponding to the input/output pads of the semiconductor device.
Claim 16
Dependent Claim
106 words
In a method of manufacturing a rigid circuit module having a conductive pattern of one or more conductive pattern layers, the improvement comprising forming, on at least one surface of the module, soft, ductile metal protuberances capable of being metallurgically bonded to the input/output pads of at least one semiconductor device; the protuberances protruding above the surface of the module far enough to compensate for variations due to the camber, planarity and overall size of both the module and the semiconductor device, and the metal protuberances being connected to the conductive pattern and formed in an array corresponding to the input/output pads of the semiconductor device.
Claim 17
Dependent Claim
60 words
The method of claim 14 wherein the outermost conductive pattern layer on the surface of the module is coated with a dielectric layer; openings are made in the dielectric layer to the conductive pattern layer, the openings corresponding to the input/output pad pattern of the semiconductor device; and the soft, ductile metal forming the protuberances is deposited in the openings.
Claim 18
Dependent Claim
23 words
The method of claim 15 wherein the dielectric layer is a temporary resist, and the temporary resist is stripped after forming the protuberances.
Claim 19
Dependent Claim
17 words
The method of claim 15 wherein the openings in the dielectric layer are made by laser ablation.
Claim 20
Dependent Claim
27 words
The method of claim 17 wherein the soft, ductile metal is selected from the group comprising aluminum, gold, indium, lead, silver, tin and alloys of these metals.
Claim 21
Dependent Claim
12 words
The method of claim 18 wherein the soft, ductile metal comprises gold.
Claim 22
Dependent Claim
127 words
In a method of making a ceramic package for a least one semiconductor device, the ceramic package having one or more conductive pattern layers the improvement comprising: coating the outermost conductive pattern with at least one thick film composition and firing the composition forming an inorganic insulating layer on the outermost conductive pattern; laser ablating openings in the dielectric layer to the conductive pattern layer, the pattern of the openings corresponding to the input/output pads of the semiconductor device, and electroplating a soft, ductile gold deposit to fill the openings and form protuberances over the openings, and positioning the semiconductor device on the circuit package with the input/output pads in contact with the protuberances and simultaneously thermocompression, thermosonically or ultrasonically bonding the input/output pads to the protuberances.
Claim 23
Dependent Claim
127 words
In a method of making a ceramic package for a least one semiconductor device, the ceramic package having one or more conductive pattern layers the improvement comprising: coating the outermost conductive pattern with at least one thick film composition and firing the composition forming an inorganic insulating layer on the outermost conductive pattern; laser ablating openings in the dielectric layer to the conductive pattern layer, the pattern of the openings corresponding to the input/output pads of the semiconductor device, and electroplating a soft, ductile gold deposit to fill the openings and form protuberances over the openings, and positioning the semiconductor device on the circuit package with the input/output pads in contact with the protuberances and simultaneously thermocompression, thermosonically or ultrasonically bonding the input/output pads to the protuberances.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |