Patent US5864663A successfully refreshed from Google Patents.
US5864663A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selectively enabled watchdog timer circuit
Assignee: Pratt and Whitney Co Inc
•
Filing: 1996-09-12
•
Granted: 1999-01-26
•
Expires: 2016-09-12
Abstract
Abstract A watchdog timer circuit includes a cyclic counter having an overflow signal that functions as a reset pulse to a microprocessor. The timer circuit includes a feature for selectively supplanting the overflow signal to enable in situ programming of the microprocessor.
Inventors
- 👤 John Stolan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F2201/00; G06F2201/88
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
102 words
An improved watchdog timer circuit for monitoring a microprocessor and resetting the microprocesser upon detection of aberrant operation that allows in situ programming of the microprocessor, the circuit comprising: a timer for generating timing pulses of specified frequency; a cyclic counter with an overflow bit which functions as a reset pulse to the microprocessor, the counter being of the type for incrementing or decrementing a stored count in accordance with the pulses of said timer; and a switching means for selectively supplanting the overflow signal of said counter with an external programming reset signal to enable in situ programming of the microprocessor.
Claim 2
Dependent Claim
102 words
An improved watchdog timer circuit for monitoring a microprocessor and resetting the microprocesser upon detection of aberrant operation that allows in situ programming of the microprocessor, the circuit comprising: a timer for generating timing pulses of specified frequency; a cyclic counter with an overflow bit which functions as a reset pulse to the microprocessor, the counter being of the type for incrementing or decrementing a stored count in accordance with the pulses of said timer; and a switching means for selectively supplanting the overflow signal of said counter with an external programming reset signal to enable in situ programming of the microprocessor.
Claim 3
Dependent Claim
30 words
The watchdog timer of claim 1, wherein said timer provides continuous timing pulses upon application of electrical power thereto, and said counter continually counts in response to the timing pulses.
Claim 4
Dependent Claim
84 words
The watchdog timer circuit of claim 2 wherein the microprocessor generates, during non aberrant operation, a signal that causes a reversal of the count direction of said counter and thereby prevents said counter from overflowing, whereby said counter repeatedly overflows when the microprocessor is in an aberrant operating mode, thereby causing a power-on reset when the microprocessor initializes in an errant state following application of power thereto and a continuous reset when the microprocessor remains in an aberrant operational state for extended temporal periods.
Claim 5
Dependent Claim
21 words
The watchdog timer circuit of claim 3 wherein the microprocessor generates said signal in response to said count of said counter.
Claim 6
Dependent Claim
79 words
The watchdog timer of claim 1, wherein the frequency of said timer and count capacity of said counter are selected such that when used in conjunction the interval preceding generation of the overflow by said counter is longer than the interval at which the microprocessor validates its operational state, yet short enough to provide a quick response window from the instant when the microprocessor enters a state of aberrant operation until the instant when the overflow signal is generated.
Claim 7
Dependent Claim
28 words
The watchdog timer of claim 1, wherein said counter further comprises an upper and a lower counting limit and generates the overflow signal upon surpassing either counting limit.
Claim 8
Dependent Claim
45 words
The watchdog timer of claim 6, wherein the microprocessor generates, in response to said count of said counter, a signal that causes a reversal of the count direction of said counter, thereby preventing said counter from surpassing either counting limit and generating said overflow signal.
Claim 9
Dependent Claim
25 words
The watchdog timer of claim 7, wherein the microprocessor generates said signal in response to a most significant bit of said count of said counter.
Claim 10
Dependent Claim
35 words
The watchdog timer circuit of claim 1 wherein the microprocessor generates, during non aberrant operation, a signal that causes a reversal of the count direction of said counter and thereby prevents said counter from overflowing.
Claim 11
Dependent Claim
21 words
The watchdog timer circuit of claim 9 wherein the microprocessor generates said signal in response to said count of said counter.
References Cited (Backward Citations)
US4234920A
Cited
US4698748A
Cited
US4628480A
Cited
US4586179A
Cited
US4809280A
Cited
US4627060A
Cited
US4708831A
Cited
US4879647A
Cited
US4837702A
Cited
US4860289A
Cited
US4982404A
Cited
US5218707A
Cited
US5341497A
Cited
US5345583A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |