Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer

Claim 1

An input/output buffer comprising: a translator circuit for translating voltage levels and including a first input terminal for receiving a signal from logic circuitry, second and third power terminals coupled to a first power supply, third and fourth power terminals coupled to a second power supply supplying a voltage different from that of said first power supply, a plurality of output terminals coupled to a plurality of output lines, and a fifth input terminal for receiving an enable signal, wherein an active signal is present on said fifth input terminal of said translator circuit, said translator circuit translates said signal on said first input terminal from a voltage of said first power supply to a voltage of said second power supply; a sequencing circuit including a plurality of input terminals coupled to said plurality of output terminals of said translator circuit, said sequencing circuit having first and second power terminals coupled to said second power supply, and having a first plurality of output terminals coupled to a first plurality of output lines and a second plurality of output terminals coupled to a second plurality of output lines, said first plurality of output lines carrying pull-up signals and said second plurality of output lines carrying pull-down signals; a driver circuit for driving signals and having first and second power terminals coupled to said second power supply, said driver circuit having a first plurality of input terminals coupled to said first plurality of output terminals of said sequencer circuit and a second plurality of output terminals of said sequencer circuit, and having a first output terminal; an input/output pad coupled to said first output terminal of said driver circuit and being connectable to an external system, said external system being coupled to said second power supply; a precondition logic circuit having first and second power terminals coupled to said second power supply, said precondition logic circuit having a third input terminal coupled to said input/output pad, and having an output terminal; a TTL detector circuit for detecting voltage levels and having a first input terminal coupled to said output terminal of said precondition logic circuit, and having a second power terminal coupled to said first power supply and a third power terminal coupled to said second power supply, said TTL detector circuit having an output terminal; a second translator circuit for translating voltage levels and having a first input terminal coupled to said output terminal of said TTL detector circuit, and having second and third power terminals coupled to said first power supply, and fourth and fifth power terminals coupled to said second power supply, said translator circuit including an output terminal; and an output terminal of said input/output buffer, said output terminal being coupled to said output terminal of said translator circuit, wherein said output terminal is coupled to said logic circuitry.