Patent US5079688A successfully refreshed from Google Patents.
Patent US5862387A successfully refreshed from Google Patents.
US5862387A
Expired / Lapsed
US
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Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller
Assignee: Intel Corp
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Filing: 1997-06-27
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Granted: 1999-01-19
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Expires: 2017-06-27
Abstract
Abstract A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
Inventors
- 👤 Neil W Songer
- 👤 James P. Kardach
- 👤 Sung-Soo Cho
- 👤 Jim S. Cheng
- 👤 Debra T. Cohen
- 👤 John W. Horigan
- 👤 Nader Raygani
- 👤 Seyed Yahay Sotoudeh
- 👤 David I. Poisner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
137 words
A controller arrangement for use in a computer system including a plurality of agents, the controller arrangement comprising: a Direct Memory Access (DMA) controller; a bus arbiter; and a logic unit, coupled to the DMA controller and to the bus arbiter, to: receive DMA requests and bus requests from the plurality of agents over a plurality of request lines, each request line being dedicated to a respective agent, and to route the DMA requests to the DMA controller and the bus requests to the bus arbiter; and receive DMA grants from the DMA controller and bus grants from the bus arbiter, and transmit the respective DMA and bus grants to at least one of the plurality of agents over at least one of a plurality of grant lines, each grant line being dedicated to a respective agent.
Claim 2
Dependent Claim
137 words
A controller arrangement for use in a computer system including a plurality of agents, the controller arrangement comprising: a Direct Memory Access (DMA) controller; a bus arbiter; and a logic unit, coupled to the DMA controller and to the bus arbiter, to: receive DMA requests and bus requests from the plurality of agents over a plurality of request lines, each request line being dedicated to a respective agent, and to route the DMA requests to the DMA controller and the bus requests to the bus arbiter; and receive DMA grants from the DMA controller and bus grants from the bus arbiter, and transmit the respective DMA and bus grants to at least one of the plurality of agents over at least one of a plurality of grant lines, each grant line being dedicated to a respective agent.
Claim 3
Dependent Claim
40 words
The controller arrangement of claim 1 including a plurality of control registers, each of which is associated with a respective agent and stores a first indication identifying the associated agent as being either a DMA agent or a bus agent.
Claim 4
Dependent Claim
50 words
The controller arrangement of claim 2 wherein the logic unit inspects the first indication in the associated register of a respective agent from which a request is received, and routes the request to either the DMA controller or the bus arbiter according to the first indication in the inspected register.
Claim 5
Dependent Claim
49 words
The controller arrangement of claim 2 wherein at least one of the plurality of control registers provides a second indication identifying at least one of a plurality of DMA channels as being assigned to an associated agent if the first indication identifies the associated agent as a DMA agent.
Claim 6
Dependent Claim
34 words
The controller arrangement of claim 2 wherein at least one of the plurality of control registers provides a third indication specifying that an associated agent can request access to a plurality of DMA channels.
Claim 7
Dependent Claim
152 words
Logic circuitry for use in a system controller of a computer system, the computer system including a plurality of agents, the logic circuitry comprising: a plurality of inputs coupled to receive resource requests from the plurality of agents via a plurality of request lines, each request line being dedicated to a respective agent; decoder circuitry to determine whether each resource request is a DMA request or a bus request; routing circuitry to route a resource request to a DMA controller if the resource request is determined by the decoder circuitry to be a DMA request, or to a bus arbiter if the resource request is determined by the decoder circuitry to be a bus request; and a plurality of outputs to transmit resource grants from the DMA controller and the bus arbiter to the plurality of agents via a plurality of grant lines, each grant line being dedicated to a respective agent.
Claim 8
Dependent Claim
152 words
Logic circuitry for use in a system controller of a computer system, the computer system including a plurality of agents, the logic circuitry comprising: a plurality of inputs coupled to receive resource requests from the plurality of agents via a plurality of request lines, each request line being dedicated to a respective agent; decoder circuitry to determine whether each resource request is a DMA request or a bus request; routing circuitry to route a resource request to a DMA controller if the resource request is determined by the decoder circuitry to be a DMA request, or to a bus arbiter if the resource request is determined by the decoder circuitry to be a bus request; and a plurality of outputs to transmit resource grants from the DMA controller and the bus arbiter to the plurality of agents via a plurality of grant lines, each grant line being dedicated to a respective agent.
Claim 9
Dependent Claim
44 words
The logic circuitry of claim 6 wherein the decoder circuitry includes a plurality of control registers, each of which is associated with a respective agent and stores a first indication identifying the associated agent as being either a DMA agent or a bus agent.
Claim 10
Dependent Claim
54 words
The logic circuitry of claim 7 wherein the decoder circuitry unit inspects the first indication in the associated register of a respective agent from which a request is received, and the routing circuitry routes the request to either the DMA controller or the bus arbiter according to the first indication in the inspected register.
Claim 11
Dependent Claim
49 words
The logic circuitry of claim 7 wherein at least one of the plurality of control registers provides a second indication identifying at least one of a plurality of DMA channels as being assigned to an associated agent if the first indication identifies the associated agent as a DMA agent.
Claim 12
Dependent Claim
46 words
The logic circuitry of claim 7 wherein at least one of the plurality of control registers provides a third indication specifying that an associated agent can request access to a plurality of DMA channels if the first indication identifies the associated agent as a DMA agent.
Claim 13
Independent Claim
160 words
A method of allocating resources in a computer system including a plurality of agents, a Direct Memory Access (DMA) controller and a bus arbiter, the method comprising the steps of: receiving a resource request from an agent at a logic unit via a request line dedicated to the agent; determining whether the resource request is a DMA request or a bus request; if the resource request is a bus request, then routing the resource request from the logic unit to the bus arbiter and routing a resource grant, responsive to the resource request, from the bus arbiter to the logic unit; if the resource request is a DMA request, then routing the resource request from the logic unit to the DMA controller and routing the resource grant, responsive to the resource request, from the DMA controller to the logic unit; and transmitting the resource grant from the logic unit to the agent via a grant line dedicated to the agent.
Claim 14
Independent Claim
160 words
A method of allocating resources in a computer system including a plurality of agents, a Direct Memory Access (DMA) controller and a bus arbiter, the method comprising the steps of: receiving a resource request from an agent at a logic unit via a request line dedicated to the agent; determining whether the resource request is a DMA request or a bus request; if the resource request is a bus request, then routing the resource request from the logic unit to the bus arbiter and routing a resource grant, responsive to the resource request, from the bus arbiter to the logic unit; if the resource request is a DMA request, then routing the resource request from the logic unit to the DMA controller and routing the resource grant, responsive to the resource request, from the DMA controller to the logic unit; and transmitting the resource grant from the logic unit to the agent via a grant line dedicated to the agent.
Claim 15
Dependent Claim
53 words
The method of claim 11 wherein the computer system includes a control register associated with the agent, the control register storing a first indication identifying the agent as being either a DMA agent or a bus agent, the step of determining comprising the step of inspecting the first indication in the control register.
Claim 16
Dependent Claim
62 words
The method of claim 12 wherein the control register provides a second indication identifying at least one of a plurality of DMA channels as being assigned to the agent if the first indication identifies the agent as a DMA agent, the method including the step of identifying the at least one DMA channel assigned to the agent based on the second indication.
Claim 17
Dependent Claim
47 words
The method of claim 12 wherein the control register provides a third indication specifying that the associated agent can request access to a plurality of DMA channels, the method including the step of identifying at least one DMA channel requested by the agent from the resource request.
Claim 18
Dependent Claim
26 words
The method of claim 14 wherein the step of identifying the at least one DMA channel comprises decoding a toggle sequence included in the resource request.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |