US4901234A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system having programmable DMA control
Assignee: Lenovo Singapore Pte Ltd
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Filing: 1987-03-27
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Granted: 1990-02-13
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Expires: 2007-03-27
Abstract
Abstract A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others, termed "programmable" DMA channels, are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA Channel assignment value with which the comparison was successful.
Inventors
- 👤 Chester A. Heath
- 👤 Jorge E. Lenta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/362; G06F13/3625; G06F13/368; G06F13/374
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
145 words
A computer system comprising: means for providing a plurality of DMA channels; a plurality of peripheral devices comprising means for requesting DMA access; means for assigning at least one of said peripheral devices to a respective dedicated one of said DMA channels for DMA access and for assigning the remainder of said peripheral devices to share the remainder of said DMA channels for DMA access; and wherein said assigning means comprises means for comparing channel priority assignment values of each one of said remainder of said peripheral devices requesting DMA access, with a predetermined programmed set of DMA channel assignment values, and means for granting one of said remainder of said peripheral devices access to a DMA channel when said one of said remainder of said peripheral devices has a channel priority assignment value corresponding to one of said predetermined programmed DMA channel assignment values.
Claim 2
Dependent Claim
145 words
A computer system comprising: means for providing a plurality of DMA channels; a plurality of peripheral devices comprising means for requesting DMA access; means for assigning at least one of said peripheral devices to a respective dedicated one of said DMA channels for DMA access and for assigning the remainder of said peripheral devices to share the remainder of said DMA channels for DMA access; and wherein said assigning means comprises means for comparing channel priority assignment values of each one of said remainder of said peripheral devices requesting DMA access, with a predetermined programmed set of DMA channel assignment values, and means for granting one of said remainder of said peripheral devices access to a DMA channel when said one of said remainder of said peripheral devices has a channel priority assignment value corresponding to one of said predetermined programmed DMA channel assignment values.
Claim 3
Dependent Claim
46 words
The computer system of claim 1, wherein said comparing means comprises means for storing said predetermined set of channel assignment values, and means for simultaneously comparing said channel priority assignment value for one of said peripherals requesting DMA access with said set of channel assignment values.
Claim 4
Dependent Claim
22 words
The computer system of claim 2, further comprising means for changing said channel assignment values for said remainder of said DMA channels.
Claim 5
Dependent Claim
188 words
A computer system comprising: a plurality of peripheral devices requiring DMA access; arbitration bus means; means in each of said peripheral devices for requesting DMA access by placing on said arbitration bus means a channel priority assignment value for the respective peripheral device; means for storing first and second sets of DMA channel assignment values, said DMA channel assignment values being fewer in number than the number of said peripherals and being equal in number to the number of DMA channels provided in said computer system, said first set of said DMA channel assignment values being fixed and corresponding to fixed predetermined ones of said channel priority assignment values, said second set DMA assignment values being programmable and allocatable among the remaining ones of said channel priority assignment values; means for comparing priority assignment values received on said arbitration bus means with said set of stored DMA channel assignment values; and means for granting DMA access to each of said peripherals whose priority assignment value is found by said comparing means to be equal to one of said DMA channel assignment values of said first and second sets.
Claim 6
Dependent Claim
188 words
A computer system comprising: a plurality of peripheral devices requiring DMA access; arbitration bus means; means in each of said peripheral devices for requesting DMA access by placing on said arbitration bus means a channel priority assignment value for the respective peripheral device; means for storing first and second sets of DMA channel assignment values, said DMA channel assignment values being fewer in number than the number of said peripherals and being equal in number to the number of DMA channels provided in said computer system, said first set of said DMA channel assignment values being fixed and corresponding to fixed predetermined ones of said channel priority assignment values, said second set DMA assignment values being programmable and allocatable among the remaining ones of said channel priority assignment values; means for comparing priority assignment values received on said arbitration bus means with said set of stored DMA channel assignment values; and means for granting DMA access to each of said peripherals whose priority assignment value is found by said comparing means to be equal to one of said DMA channel assignment values of said first and second sets.
Claim 7
Dependent Claim
32 words
The computer system of claim 4, wherein said storing means comprises for each of said programmable DMA channel assignment values a register programmable by a central processing unit of said computer system.
Claim 8
Dependent Claim
30 words
The computer system of claim 5, wherein said storing means comprises, for each of said fixed DMA channel assignment values, means for fixedly inputting the respective DMA channel assignment value.
Claim 9
Independent Claim
159 words
A method for controlling DMA access in a computer system, comprising the steps of: assigning to each of a plurality of peripherals requiring DMA access a channel priority assignment value; fixedly storing a first set of DMA channel assignment values for DMA channels dedicated to respective peripheral devices, and programmably storing a second set of DMA channel assignment values for DMA channels shared among a plurality of peripheral devices; transmitting onto a bus from each of said peripherals requesting DMA access its channel priority assignment value; arbitrating on said bus to determine a highest channel priority assignment value of peripherals concurrently requesting DMA access; comparing said highest channel priority assignment value with said first and second sets of DMA channels assignment values; and granting access to a respective DMA channel to the corresponding peripheral device when said highest channel priority assignment value is equal to one of said DMA channel assignment values contained in said first and second sets.
Claim 10
Independent Claim
159 words
A method for controlling DMA access in a computer system, comprising the steps of: assigning to each of a plurality of peripherals requiring DMA access a channel priority assignment value; fixedly storing a first set of DMA channel assignment values for DMA channels dedicated to respective peripheral devices, and programmably storing a second set of DMA channel assignment values for DMA channels shared among a plurality of peripheral devices; transmitting onto a bus from each of said peripherals requesting DMA access its channel priority assignment value; arbitrating on said bus to determine a highest channel priority assignment value of peripherals concurrently requesting DMA access; comparing said highest channel priority assignment value with said first and second sets of DMA channels assignment values; and granting access to a respective DMA channel to the corresponding peripheral device when said highest channel priority assignment value is equal to one of said DMA channel assignment values contained in said first and second sets.
Claim 11
Dependent Claim
25 words
The method of claim 7, wherein said step of comparing comprises simultaneously comparing said highest channel priority assignment value with said first and second sets.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |