Patent US2178858A successfully refreshed from Google Patents.
US4437157A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic subchannel allocation
Assignee: Unisys Corp
•
Filing: 1981-04-20
•
Granted: 1984-03-13
•
Expires: 2001-04-20
Abstract
Abstract An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture. A random access memory (RAM) is employed which provides the correlation between each I/O subchannel and the I/O channel to which it has been allocated. The RAM is called the Channel Descriptor Stack (CDS). The CDS may be loaded using a variety of techniques. In the preferred embodiment, the CDS is loaded via a specialized processor, called a system support processor (SSP), which also performs those tasks normally associated with system control (e.g., system reconfiguration, interface to the system operator, casualty recovery, etc.).
Inventors
- 👤 Jerome J. Witalka
- 👤 Duane G. Kurth
- 👤 David J. Baber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
435 words
In a computer with means for initializing the operation of said computer and with an Input/Output unit having a plurality of Input/Output channels wherein one or more of said Input/Output channels is each capable of maintaining a plurality of independent asynchronous buffered Input/Output transfers and having a controller capable of controlling said plurality of asynchronous buffer Input/Output transfers through the use of a plurality of Input/Output subchannels wherein each of said plurality of independent asynchronous buffered Input/Output transfers is controlled through the use of a different one of said plurality of Input/Output subchannels, the improved apparatus for allocating each of said plurality of Input/Output subchannels to one of said plurality of Input/Output channels and for conducting buffered Input/Output transfers operative in accordance with Externally Specified Indexing (ESI), an improvement to such apparatus according that each of a plurality of Input/Output subchannels--each said Input/Output subchannels being a designation of the hardware resource, specifically the Buffer Control Words (BCWs) contained within I/O General Register (IGR), which designated resource is dedicated to the control of communication upon an Input/Output channel with a corresponding one of a plurality of peripheral devices which share said Input/Output channel--are allocable, meaning assignable, to each of a plurality of Input/Output channels--each said Input/Output channel being a bandwidth limited physical communication path between said Input/Output apparatus and a multiplicity of peripheral devices,--said inprovement comprising: random access memory means, called a Channel Descriptor Stack (CDS), for storing an allocation of each of said plurality of Input/Output channels to a one of said plurality on Input/Output subchannels, wherein said storing means has a one addressable location corresponding to each of said plurality of Input/Output subchannels: loading means, called a System Support Processor (SPS), for entering said allocation of each of said plurality of Input/Output channels to said one of said plurality of Input/Output subchannels into said storing means; and control means responsively coupled to said storing means for causing each of said buffered Input/Output transfers as occur upon each of said plurality of Input/Output subchannels to physically transpire upon said allocated one of said plurality of Input/Output channels; whereby said hardware resource associated with each said Input/Output subchannels, which resource is dedicated to the control of communication upon an Input/Output channel, is allocated, meaning distributed, in accordance with said stored allocation to a one of said bandwidth limited physical I/O channel communication paths; whereby the designation of hardware resource within an Input/Output apparatus operative in accordance with Externally Specified Indexing is allocated, meaning distributed, to ones of bandwidth limited physical I/O channel communication paths in accordance with stores within a random access memory means for storing.
Claim 2
Dependent Claim
435 words
In a computer with means for initializing the operation of said computer and with an Input/Output unit having a plurality of Input/Output channels wherein one or more of said Input/Output channels is each capable of maintaining a plurality of independent asynchronous buffered Input/Output transfers and having a controller capable of controlling said plurality of asynchronous buffer Input/Output transfers through the use of a plurality of Input/Output subchannels wherein each of said plurality of independent asynchronous buffered Input/Output transfers is controlled through the use of a different one of said plurality of Input/Output subchannels, the improved apparatus for allocating each of said plurality of Input/Output subchannels to one of said plurality of Input/Output channels and for conducting buffered Input/Output transfers operative in accordance with Externally Specified Indexing (ESI), an improvement to such apparatus according that each of a plurality of Input/Output subchannels--each said Input/Output subchannels being a designation of the hardware resource, specifically the Buffer Control Words (BCWs) contained within I/O General Register (IGR), which designated resource is dedicated to the control of communication upon an Input/Output channel with a corresponding one of a plurality of peripheral devices which share said Input/Output channel--are allocable, meaning assignable, to each of a plurality of Input/Output channels--each said Input/Output channel being a bandwidth limited physical communication path between said Input/Output apparatus and a multiplicity of peripheral devices,--said inprovement comprising: random access memory means, called a Channel Descriptor Stack (CDS), for storing an allocation of each of said plurality of Input/Output channels to a one of said plurality on Input/Output subchannels, wherein said storing means has a one addressable location corresponding to each of said plurality of Input/Output subchannels: loading means, called a System Support Processor (SPS), for entering said allocation of each of said plurality of Input/Output channels to said one of said plurality of Input/Output subchannels into said storing means; and control means responsively coupled to said storing means for causing each of said buffered Input/Output transfers as occur upon each of said plurality of Input/Output subchannels to physically transpire upon said allocated one of said plurality of Input/Output channels; whereby said hardware resource associated with each said Input/Output subchannels, which resource is dedicated to the control of communication upon an Input/Output channel, is allocated, meaning distributed, in accordance with said stored allocation to a one of said bandwidth limited physical I/O channel communication paths; whereby the designation of hardware resource within an Input/Output apparatus operative in accordance with Externally Specified Indexing is allocated, meaning distributed, to ones of bandwidth limited physical I/O channel communication paths in accordance with stores within a random access memory means for storing.
Claim 3
Dependent Claim
29 words
A computer according to claim 1 wherein the storing means further comprises: a random access memory having one addressable location corresponding to each of said plurality of Input/Output subchannels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |