Network switching system including a zero-delay output buffer

Claim 1

A network switching system including a clock generator which generates an input clock signal of predetermined frequency, the system comprising: a network processor module responsive to the input clock signal; and a plurality of line card modules each attached to a physical communication media and responsive to the input clock signal, wherein said network processor module and said plurality of line card modules each includes an interface circuit which includes a zero-delay output buffer comprising a modified phase-locked loop (PLL) circuit configured to receive the input clock signal and to deliver output clock signals having a higher frequency than said predetermined frequency to a plurality of data output buffer paths via a clock distribution tree having an associated absolute propagation delay, said modified PLL circuit containing circuitry inserted within a feedback loop thereof, the circuitry including a divider circuit clocked by one of said output clock signals for generating from said one of said output clock signals another signal of said predetermined frequency for being input to a register clocked by another one of said output clock signals, the circuitry also replicating components of each of the plurality of data output buffer paths and being configured to essentially entirely compensate for said associated absolute propagation delay, and whereby the zero-delay output buffer reduces clock skew among the data output buffer paths of the plurality of modules of the system, said divider circuit not being a replicated component of the data output buffer paths.