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US5858834A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming cylindrical capacitor lower plate in semiconductor device

Assignee: Longitude Semiconductor SARL
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Filing: 1997-02-28
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Granted: 1999-01-12
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Expires: 2017-02-28
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Abstract

Abstract In a method for forming a cylindrical capacitor lower plate in a semiconductor device, a first insulating film, a first conducting film and a second insulating film are formed on a principal surface of a semiconductor substrate in the named order. A patterned photoresist film is formed on the second insulating film, and the second insulating film is patterned by an anisotropic etching using the photoresist film as a mask. After the photoresist film is removed, the first conducting film is patterned by an etching using the patterned second insulating film as a mask. Thereafter, a second conducting film is deposited on a whole surface, and then, the second conducting film is anisotropically etched so that a remaining second conducting film is left on a side surface of the patterned first conducting film. The patterned second insulating film is removed, so that the remaining second conducting film is left in the form of a sidewall which is upright from a periphery of the patterned first conducting film.

Inventors

  • 👤 Toshiyuki Hirota
  • 👤 Kiyotaka Sakamoto
  • 👤 Shuji Fujiwara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 345 words
A method for forming a lower plate of a cylinder type stacked structure capacitor in a semiconductor device, comprising: depositing a first insulating film on a principal surface of a semiconductor substrate in which at least one MOS transistor is formed; forming a contact hole which penetrates said first insulating film to reach said semiconductor substrate; depositing a first conducting film to fill said contact hole and to cover said first insulating film; depositing on said first conducting film, a second insulating film which is formed of a silicon oxide film containing at least one impurity selected from the group consisting of V-group elements and III-group elements, and which can be selectively etched against said first insulating film; conducting a heat treatment after said second insulating film is deposited; forming a resist film on said second insulating film and at a position directly above said contact hole; conducting a first anisotropic etching using said photoresist film as a mask, so as to selectively etch said second insulating film, thereby to deposit an etching reaction product and to form a patterned second insulating film in alignment with said resist film; removing said reaction product deposited and said resist film; etching selectively said first conducting film using said patterned film as a mask, to form a patterned first conducting film in alignment with said patterned second insulating film, and to expose said first insulating film; depositing a second conducting film on a whole surface; conducting a second anisotropic etching to said second conducting film so that a remaining second conducting film is left only on a side surface of said patterned second insulating film and said patterned first conducting film thereunder, said remaining second conducting film being in contact with said patterned first conducting film; and selectively removing said patterned second insulating film, whereby said patterned first conducting film constitutes a base portion of a cylindrical capacitor lower plate, and said remaining second conducting film constitutes a sidewall portion of said cylindrical capacitor lower plate, said sidewall portion being upright from a periphery of said base portion.
Claim 2
Independent Claim 345 words
A method for forming a lower plate of a cylinder type stacked structure capacitor in a semiconductor device, comprising: depositing a first insulating film on a principal surface of a semiconductor substrate in which at least one MOS transistor is formed; forming a contact hole which penetrates said first insulating film to reach said semiconductor substrate; depositing a first conducting film to fill said contact hole and to cover said first insulating film; depositing on said first conducting film, a second insulating film which is formed of a silicon oxide film containing at least one impurity selected from the group consisting of V-group elements and III-group elements, and which can be selectively etched against said first insulating film; conducting a heat treatment after said second insulating film is deposited; forming a resist film on said second insulating film and at a position directly above said contact hole; conducting a first anisotropic etching using said photoresist film as a mask, so as to selectively etch said second insulating film, thereby to deposit an etching reaction product and to form a patterned second insulating film in alignment with said resist film; removing said reaction product deposited and said resist film; etching selectively said first conducting film using said patterned film as a mask, to form a patterned first conducting film in alignment with said patterned second insulating film, and to expose said first insulating film; depositing a second conducting film on a whole surface; conducting a second anisotropic etching to said second conducting film so that a remaining second conducting film is left only on a side surface of said patterned second insulating film and said patterned first conducting film thereunder, said remaining second conducting film being in contact with said patterned first conducting film; and selectively removing said patterned second insulating film, whereby said patterned first conducting film constitutes a base portion of a cylindrical capacitor lower plate, and said remaining second conducting film constitutes a sidewall portion of said cylindrical capacitor lower plate, said sidewall portion being upright from a periphery of said base portion.
Claim 3
Dependent Claim 17 words
A method claimed in claim 1 wherein said first conducting film is formed of a silicon film.
Claim 4
Dependent Claim 30 words
A method claimed in claim 1 wherein said first anisotropic etching is conducted by a reactive ion etching using a mixed gas containing CF 4 gas and CHF 3 gas.
Claim 5
Dependent Claim 18 words
A method claimed in claim 1 wherein said first insulating film is formed of a silicon nitride film.
Claim 6
Dependent Claim 16 words
A method claimed in claim 4 wherein said second insulating film being formed of borophosphosilicate glass.
Claim 7
Dependent Claim 16 words
A method claimed in claim 4 wherein said second insulating film being formed of phosphosilicate glass.
Claim 8
Dependent Claim 18 words
A method claimed in claim 1 wherein said first insulating film is formed of an undoped silicon film.
Claim 9
Dependent Claim 17 words
A method as claimed in claim 7 wherein said second insulating film being formed of borophosphosilicate glass.
Claim 10
Dependent Claim 16 words
A method claimed in claim 7 wherein said second insulating film being formed of phosphosilicate glass.
Claim 11
Dependent Claim 19 words
A method claimed in claim 7 wherein a heat treatment is conducted after said first insulating film is deposited.
Claim 12
Dependent Claim 36 words
A method claimed in claim 1 wherein said patterned second insulating film is removed by an etching agent selected from the group consisting of a heated phosphoric acid aqueous solution and a hydrogen fluoride aqueous solution.
Claim 13
Dependent Claim 37 words
A method claimed in claim 1 further including the step of forming concavities and convexities on a surface of said cylindrical capacitor lower plate constituted of said patterned first conducting film and said remaining second conducting film.

References Cited (Backward Citations)

US5284787A Cited
JPH05136371A Cited
US5448512A Cited
US5408114A Cited
JPH0629463A Cited
DE4328510A1 Cited
US5481127A Cited
US5476807A Cited
DE4423818A1 Cited
DE4446983A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-01-11 2002-07-13 2003-01-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-01-11 2006-07-13 2007-01-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-01-11 2010-07-13 2011-01-12 $7700.00 Window Closed / Lapsed

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