Abstract The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.
A semiconductor memory device having a cylindrical capacitor, comprising: a memory cell array including said cylindrical capacitor; said cylindrical capacitor having a storage node including a bottom conductive portion and a sidewall conductive portion provided along a periphery of said bottom conductive portion and extending upwardly, a peripheral circuit; a horizontal member extending horizontally and made of the same material as said bottom conductive portion, provided on a boundary between said memory cell array and said peripheral circuit; a vertical member extending upwardly and made of the same material as said sidewall conductive portion, provided to be connected to said horizontal member; and an oxide film formed on said horizontal member and being adjacent to said vertical member and having a thickness substantially equal to a height of said vertical member.
Claim 2
Dependent Claim
131 words
A semiconductor memory device having a cylindrical capacitor, comprising: a memory cell array including said cylindrical capacitor; said cylindrical capacitor having a storage node including a bottom conductive portion and a sidewall conductive portion provided along a periphery of said bottom conductive portion and extending upwardly, a peripheral circuit; a horizontal member extending horizontally and made of the same material as said bottom conductive portion, provided on a boundary between said memory cell array and said peripheral circuit; a vertical member extending upwardly and made of the same material as said sidewall conductive portion, provided to be connected to said horizontal member; and an oxide film formed on said horizontal member and being adjacent to said vertical member and having a thickness substantially equal to a height of said vertical member.