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US5856946A
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Memory cell programming with controlled current injection
Assignee: Monterey Research LLC
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Filing: 1997-04-09
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Granted: 1999-01-05
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Expires: 2017-04-09
Abstract
Abstract A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.
Inventors
- 👤 Vei-Han Chan
- 👤 Sameer Haddad
- 👤 Chi Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
173 words
A memory device, comprising: a memory cell having a control gate having a corresponding voltage V g , a floating gate formed over a substrate having a corresponding voltage V fg , and a first region and a second region formed in the substrate with a channel region therebetween; and circuitry that applies a time-varying voltage V g (t) to the control gate during a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory cell; wherein said time-varying voltage V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from a drain region of one of said first and second regions to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 2
Dependent Claim
173 words
A memory device, comprising: a memory cell having a control gate having a corresponding voltage V g , a floating gate formed over a substrate having a corresponding voltage V fg , and a first region and a second region formed in the substrate with a channel region therebetween; and circuitry that applies a time-varying voltage V g (t) to the control gate during a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory cell; wherein said time-varying voltage V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from a drain region of one of said first and second regions to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 3
Dependent Claim
14 words
The memory device of claim 1, wherein the time-varying voltage comprises a ramp function.
Claim 4
Dependent Claim
21 words
The memory device of claim 2, wherein the time-varying voltage comprises a steadily increasing staircase function that approximates the ramp function.
Claim 5
Dependent Claim
29 words
The memory device of claim 1, wherein the time-varying voltage has a slope selected to offset the effects of electron accumulation on the floating gate during the programming cycle.
Claim 6
Dependent Claim
39 words
The memory device of claim 1, wherein: the memory cell has a threshold voltage: and the time-varying voltage has a slope selected to maintain a linear increase in the threshold voltage throughout the programming cycle on the memory cell.
Claim 7
Dependent Claim
23 words
The memory device of claim 1, wherein: the time varying voltage rises above 12 volts during the programming cycle on the memory cell.
Claim 8
Dependent Claim
153 words
A memory device, comprising: a flash memory cell having, a control gate, a floating gate having a corresponding voltage V fg ; a channel region; and a ramp voltage generator in communication with the control gate, the ramp voltage generator applies an increasing time-varying voltage V g (t) to the control gate throughout a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory wherein said time-varying voltage V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from a drain region to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 9
Dependent Claim
153 words
A memory device, comprising: a flash memory cell having, a control gate, a floating gate having a corresponding voltage V fg ; a channel region; and a ramp voltage generator in communication with the control gate, the ramp voltage generator applies an increasing time-varying voltage V g (t) to the control gate throughout a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory wherein said time-varying voltage V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from a drain region to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 10
Dependent Claim
15 words
The memory device of claim 7, wherein the increasing time-varying voltage comprises a ramp function.
Claim 11
Dependent Claim
22 words
The memory device of claim 7, wherein the increasing time-varying voltage comprises a steadily increasing staircase function that approximates the ramp function.
Claim 12
Dependent Claim
39 words
The memory device of claim 7, wherein: the memory cell has a threshold voltage; and the time-varying voltage has a slope selected to maintain a linear increase in the threshold voltage throughout a programming cycle on the memory cell.
Claim 13
Dependent Claim
23 words
The memory device of claim 7, wherein: the time varying voltage rises above 12 volts during the programming cycle on the memory cell.
Claim 14
Independent Claim
162 words
A method for programming a flash memory cell, the flash memory cell including a source, a drain, a control gate, a floating gate having a corresponding voltage V fg ; and a channel region, the method comprising the steps of: applying a first voltage to said drain; and applying an increasing time-varying second voltage V g (t) to the control gate during a programming cycle on the flash memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the second voltage varying throughout the programming cycle on the flash memory cell wherein said V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from said drain to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 15
Independent Claim
162 words
A method for programming a flash memory cell, the flash memory cell including a source, a drain, a control gate, a floating gate having a corresponding voltage V fg ; and a channel region, the method comprising the steps of: applying a first voltage to said drain; and applying an increasing time-varying second voltage V g (t) to the control gate during a programming cycle on the flash memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the second voltage varying throughout the programming cycle on the flash memory cell wherein said V g (t) is applied such that said floating gate voltage V fg is represented by α d *V d +α g *(V g -ΔV t ), where α d is a coupling coefficient from said drain to said floating gate, and α g is a coupling coefficient from said control gate to said floating gate.
Claim 16
Dependent Claim
14 words
A method according to claim 12, further including the step of: grounding the source.
Claim 17
Dependent Claim
15 words
A method according to claim 12, wherein: the increasing time-varying voltage comprises a ramp function.
Claim 18
Dependent Claim
22 words
A method according to claim 12, wherein: the increasing time-varying voltage comprises a steadily increasing staircase function that approximates the ramp function.
Claim 19
Dependent Claim
39 words
A method according to claim 12, wherein: the memory cell has a threshold voltage; and the time-varying voltage has a slope selected to maintain a linear increase in the threshold voltage throughout a programming cycle on the memory cell.
References Cited (Backward Citations)
US5258949A
Cited
US5615153A
Cited
US5553020A
Cited
US5508958A
Cited
US5638320A
Cited
US5481492A
Cited
US5590076A
Cited
US5687118A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-01-04 | 2002-07-06 | 2003-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-04 | 2006-07-06 | 2007-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-04 | 2010-07-06 | 2011-01-05 | $7700.00 | Window Closed / Lapsed |