Channel hot-carrier page write

Claim 2

A low-energy write mode flash EEPROM, comprising: an array of floating gate flash EEPROM memory cells formed on a substrate in rows and columns, each cell having a source, a drain, a channel between the source and the drain, a floating gate extending between the source and the drain above the channel, and a control gate extending between the source and the drain above the floating gate, the control gates of respective rows being connected to respective word select lines, the memory cell sources for at least one row of memory cells being coupled to a common source line, and the memory cell drains of respective columns being connected to respective bit select lines; the memory cells having a high core doping to optimize cell programming by hot carrier injection into the floating gates of selected memory cells; a circuit for limiting a programming drain current to less than 10 μA per memory cell, the limited cell drain current resulting in a high programming efficiency; and a selected row of memory cells being programmable within a shortened row programming interval having a predetermined value less than 100 μS, whereby the limited drain current and the shortened row programming interval define a low-energy write mode of operation for the flash EEPROM.

Claim 3

The low-energy write mode flash EEPROM as set forth in claim 1, further including the at least one row of memory cells having 1024 cells and defining a page.

Claim 4

The low-energy write mode flash EEPROM as set forth in claim 1, wherein the programming efficiency has a range from 10 -6 to 10 -4 .

Claim 5

The low-energy write mode flash EEPROM as set forth in claim 1, wherein the sources and the common source line define a parasitic capacitance and the flash EEPROM further including means for precharging said defined capacitance for minimizing an AC component of the programming drain current.

Claim 6

The low-energy write mode flash EEPROM as set forth in claim 1, further including at least one charge pump connected to derive a drain programming voltage level from a +V CC input line.

Claim 7

The low-energy write mode flash EEPROM as set forth in claim 5, wherein the drain programming voltage level is between 6.5 and 6.8 VDC and the core dose is 2.2×10 13 #cm -2 .

Claim 8

The low-energy write mode flash EEPROM as set forth in claim 5, wherein the drain programming voltage level is between 5.1 and 5.5 VDC and the core dose is 4.6×10 13 #cm -2 .

Claim 9

The low-energy write mode flash EEPROM as set forth in claim 5, wherein the drain programming voltage level is between 5.0 and 5.26 VDC and the core dose is 5.4×10 13 #cm -2 .

Claim 10

The low-energy write mode flash EEPROM as set forth in claim 5, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 4×10 15 #cm -2 .

Claim 11

The low-energy write mode flash EEPROM as set forth in claim 5, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 6×10 15 #cm -2 .

Claim 12

The low-energy write mode flash EEPROM as set forth in claim 5, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 8×10 15 #cm -2 .

Claim 13

A low-energy programming flash EEPROM, comprising: an array of flash EEPROM memory cells formed to define columns and rows, the array including a common source line extending along at least one of the rows and having a stray capacitance, a common row select line extending along the at least one row, and a plurality of bit lines extending along respective columns, each memory cell including an N-type source region coupled to the common source line, a control gate coupled to the common row select line, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines and defining a memory cell drain junction, each drain junction being optimized for hot carrier injection, and each memory cell being programmable by injection of hot electrons into the floating gate from the cell drain junction; a +V CC input line; at least one charge pump connected to the +V CC input line for providing a predetermined drain voltage level via the bit lines to a selected row of memory cells; a source line precharge circuit connected for precharging the common source line stray capacitance to a predetermined source voltage level; a current limiting circuit defining a programming interval and being connected for limiting a memory cell channel current to less than 10 μA for each memory cell of the selected row during said interval, the interval having a predetermined duration less than 100 μS; and the memory cell defining a low-energy programming mode of operation having a high programming efficiency and in which memory cell programming channel current is supplied by the at least one charge pump.

Claim 14

A low-energy programming flash EEPROM, comprising: an array of flash EEPROM memory cells formed to define columns and rows, the array including a common source line extending along at least one of the rows and having a stray capacitance, a common row select line extending along the at least one row, and a plurality of bit lines extending along respective columns, each memory cell including an N-type source region coupled to the common source line, a control gate coupled to the common row select line, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines and defining a memory cell drain junction, each drain junction being optimized for hot carrier injection, and each memory cell being programmable by injection of hot electrons into the floating gate from the cell drain junction; a +V CC input line; at least one charge pump connected to the +V CC input line for providing a predetermined drain voltage level via the bit lines to a selected row of memory cells; a source line precharge circuit connected for precharging the common source line stray capacitance to a predetermined source voltage level; a current limiting circuit defining a programming interval and being connected for limiting a memory cell channel current to less than 10 μA for each memory cell of the selected row during said interval, the interval having a predetermined duration less than 100 μS; and the memory cell defining a low-energy programming mode of operation having a high programming efficiency and in which memory cell programming channel current is supplied by the at least one charge pump.

Claim 15

The low-energy programming flash EEPROM as set forth in claim 12, wherein the selected row of memory cells is extended to include at least 1024 memory cells, the extended row defining a page.

Claim 16

The low-energy programming flash EEPROM as set forth in claim 12, wherein the programming efficiency has a range from 10 -6 to 10 -4 .

Claim 17

The low-energy programming flash EEPROM as set forth in claim 12, wherein the optimization for hot carrier injection results from a high core dose.

Claim 18

The low-energy programming flash EEPROM as set forth in claim 15, wherein the drain programming voltage level is between 6.5 and 6.8 VDC and the core dose is 2.2×10 13 #cm -2 .

Claim 19

The low-energy programming flash EEPROM as set forth in claim 15, wherein the drain programming voltage level is between 5.1 and 5.5 VDC and the core dose is 4.6×10 13 #cm -2 .

Claim 20

The low-energy programming flash EEPROM as set forth in claim 15, wherein the drain programming voltage level is between 5.0 and 5.26 VDC and the core dose is 5.4×10 13 #cm -2 .

Claim 21

The low-energy programming flash EEPROM as set forth in claim 15, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 4×10 15 #cm -2 .

Claim 22

The low-energy programming flash EEPROM as set forth in claim 15, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 6×10 15 #cm -2 .

Claim 23

The low-energy programming flash EEPROM as set forth in claim 15, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 8×10 15 #cm -2 .

Claim 24

A flash EEPROM memory system comprising: an array of flash EEPROM floating gate memory cells configured in columns and rows, each memory cell having an N+ drain region, an N+ source region, the source and drain regions being separated by a channel region, a floating gate extending above the channel region between the drain and source regions, a control extending above the floating gate, the drain regions of each column being connected to a common bit select line, the controls of each row being connected to a common page select line, the sources of at least each page being connected to a common source line, the memory cells having a high core doping for optimizing programming by hot carrier injection into the floating gates, the common source line connected to a circuit for biasing each memory cell source region to define a low energy operating mode having a high programming efficiency and a shortened programming cycle; a cache buffer connected to receive data input lines and providing temporary storage for at least one page of data, the cache buffer having data output lines for controlling the at least one page of bit lines during the programming cycle; address and control logic circuits for storing the data received on the data input lines into separate locations of the cache buffer and for accessing the contents of the cache buffer one page at a time for controlling the bit lines during the programming cycle for writing one page of data from the cache buffer into a selected page of the array of memory cells, whereby the high programming efficiency permits a page of data to be written into a page of the memory cell array during the shortened programming cycle.

Claim 25

A flash EEPROM memory system comprising: an array of flash EEPROM floating gate memory cells configured in columns and rows, each memory cell having an N+ drain region, an N+ source region, the source and drain regions being separated by a channel region, a floating gate extending above the channel region between the drain and source regions, a control extending above the floating gate, the drain regions of each column being connected to a common bit select line, the controls of each row being connected to a common page select line, the sources of at least each page being connected to a common source line, the memory cells having a high core doping for optimizing programming by hot carrier injection into the floating gates, the common source line connected to a circuit for biasing each memory cell source region to define a low energy operating mode having a high programming efficiency and a shortened programming cycle; a cache buffer connected to receive data input lines and providing temporary storage for at least one page of data, the cache buffer having data output lines for controlling the at least one page of bit lines during the programming cycle; address and control logic circuits for storing the data received on the data input lines into separate locations of the cache buffer and for accessing the contents of the cache buffer one page at a time for controlling the bit lines during the programming cycle for writing one page of data from the cache buffer into a selected page of the array of memory cells, whereby the high programming efficiency permits a page of data to be written into a page of the memory cell array during the shortened programming cycle.

Claim 26

The flash EEPROM memory system as set forth in claim 22, wherein the page includes at least 1024 bits.

Claim 27

The flash EEPROM memory system as set forth in claim 22, wherein the programming efficiency has a range from 10 -6 to 10 -4 .

Claim 28

The flash EEPROM memory system as set forth in claim 22, further including at least one charge pump connected to derive a drain programming voltage level from a +V CC input line.

Claim 29

The flash EEPROM memory system as set forth in claim 25, wherein the drain programming voltage level is between 6.5 and 6.8 VDC and the core dose is 2.2×10 13 #cm -2 .

Claim 30

The flash EEPROM memory system as set forth in claim 25, wherein the drain programming voltage level is between 5.1 and 5.5 VDC and the core dose is 4.6×10 13 #cm -2 .

Claim 31

The flash EEPROM memory system as set forth in claim 25, wherein the drain programming voltage level is between 5.0 and 5.26 VDC and the core dose is 5.4×10 13 #cm -2 .

Claim 32

The flash EEPROM memory system as set forth in claim 25, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 4×10 15 #cm -2 .

Claim 33

The flash EEPROM memory system as set forth in claim 25, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 6×10 15 #cm -2 .

Claim 34

The flash EEPROM memory system as set forth in claim 25, further including the memory cell drain having a high drain doping concentration, and wherein the drain dose is 8×10 15 #cm -2 .