Fast flash EPROM programming and pre-programming circuit design

Claim 1

A floating gate memory integrated circuit, comprising: a plurality of subarrays, having N columns and M rows of floating gate storage transistors, storage transistors in the subarrays having respective control gates, sources and drains; an address generator, coupled to the K subarrays, to generate address signals to access selected subarrays and selected floating gate storage transistors; a plurality of wordlines, coupled to the control gates of storage cells in respective rows; a plurality of global bitlines, coupled to respective columns of storage cells; a plurality of local bitlines, each coupled to the drains of the storage cells in a respective column; a first selector, coupled to the address generator to selectively connect the local bitlines in a subarray of storage cells to the corresponding global bitlines in response to the address signals; a plurality of local virtual ground lines, each coupled to the sources of storage cells a respective column; a second selector to connect the local virtual ground lines in a subarray of storage cells with a virtual ground terminal; column select circuits, coupled to the global bitlines and the address generator to selectively enable access to columns of storage cells in response to the address signals; programming circuits, coupled to the plurality of wordlines, the plurality of bitlines and the plurality of virtual ground lines, to supply a gate programming potential to selected wordlines,--a reference potential to the virtual ground lines,--and a data-in potential to selected bitlines to program selected floating gate storage transistors in response to the address signals; and control circuits, coupled to the programming circuits to vary the gate programming potential during a programming interval as function of time in order to decrease time required to program the selected floating gate transistor the gate programming potential during the programming interval including a pulse, the pulse including a first part in which the gate programming potential increases to a first potential high enough to induce hot electron injection, and a second part in which the gate programming potential increases from the first potential to a second potential higher than the first potential.