Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures

Claim 2

A processor which supports first and second architectures having separate and distinct modes of operation and separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction; a memory management unit determining and indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and indicating said architectural context of a program responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said program being read from memory as being either code for said first architecture or code for said second architecture, said control unit controlling said instruction decoder and said memory management unit to dynamically switch between address translation for a mode of operation corresponding to the first or second architectures and executing one or more decoded instructions according to said mode of operation.

Claim 3

The processor recited in claim 1 wherein the memory management unit comprises a mode control mechanism controlled by said control means for controlling which of first or second architectural translation methods is to be used by a memory management unit when translating an effective address to a virtual address.

Claim 4

The processor recited in claim 2 wherein the mode control mechanism controls an instruction fetch and decode mechanism of the processor so that instructions of said first and second architectures are fetched and aligned for proper decoding by said instruction decoder.

Claim 5

The processor recited in claim 3 wherein said memory management unit reads a page mode control bit from a page table entry for said second architecture, said page mode control bit being supplied to said control means to control address translation by said memory management unit.

Claim 6

A processor which supports first and second architectures with separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: a memory management unit determining and indicating whether each instruction in memory is of said first or second architecture, said memory management unit further performing address translation from virtual to real addresses for said first and second architectures; an instruction decoder directly receiving instructions from memory and decoding said received instructions as belonging to the instruction set of said first or said second architecture depending on an architectural context for each said received instruction; and control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for said first or said second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises: an architectural context control mechanism for controlling which architectural context the processor operates under, said architectural context control mechanism controlling an architectural translation method to be used by the memory management unit of the processor when translating an effective address to a virtual address, said architectural context control mechanism further controlling instruction fetch and decode logic of the processor, said architectural context control mechanism further controlling an execution context of process and resources, and said architectural context control mechanism further controlling an interrupt and exception mechanism of the processor, and a qualifying mode control mechanism for enabling extensions and limitations to the two architectures, said extensions and limitations allowing a single address translation mechanism to map addresses for one architecture onto translation of addresses of another architecture and a unified interrupt and exception mechanism handling asynchronous interrupts and page translation and protection related exceptions regardless of the architectural context in effect when an interrupt or exception occurs.

Claim 7

A processor which supports first and second architectures with separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: a memory management unit determining and indicating whether each instruction in memory is of said first or second architecture, said memory management unit further performing address translation from virtual to real addresses for said first and second architectures; an instruction decoder directly receiving instructions from memory and decoding said received instructions as belonging to the instruction set of said first or said second architecture depending on an architectural context for each said received instruction; and control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for said first or said second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises: an architectural context control mechanism for controlling which architectural context the processor operates under, said architectural context control mechanism controlling an architectural translation method to be used by the memory management unit of the processor when translating an effective address to a virtual address, said architectural context control mechanism further controlling instruction fetch and decode logic of the processor, said architectural context control mechanism further controlling an execution context of process and resources, and said architectural context control mechanism further controlling an interrupt and exception mechanism of the processor, and a qualifying mode control mechanism for enabling extensions and limitations to the two architectures, said extensions and limitations allowing a single address translation mechanism to map addresses for one architecture onto translation of addresses of another architecture and a unified interrupt and exception mechanism handling asynchronous interrupts and page translation and protection related exceptions regardless of the architectural context in effect when an interrupt or exception occurs.

Claim 8

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction, wherein said instruction decoder comprises: first decoding means for decoding instructions for said first instruction set, second decoding means for decoding instructions for said second instruction set, and selection means for selecting decoded instructions from said first decoding means or decoded instructions from said second decoding means; a memory management unit determining and indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means controlling the selection means of said instruction decoder and controlling said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context.

Claim 9

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction, wherein said instruction decoder comprises: first decoding means for decoding instructions for said first instruction set, second decoding means for decoding instructions for said second instruction set, and selection means for selecting decoded instructions from said first decoding means or decoded instructions from said second decoding means; a memory management unit determining and indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means controlling the selection means of said instruction decoder and controlling said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context.

Claim 10

The processor recited in claim 6 wherein said first and second decoding means decode simple instructions of said first and second architectures, simple instructions being instructions that map into a basic operation class and can be handled by a single execution unit, said instruction management means further comprising: third decoding means for decoding complex instructions of said first instruction set; fourth decoding means for decoding complex instructions of said second instruction set; second selection means controlled by said control means for selecting decoded instructions from said third or fourth decoding means; second mapping means receiving an output of said second selection means for mapping decoded instructions from said third or fourth decoding means for mapping said decoded instructions to multiple, simple instructions of said second instruction set; and third selection means responsive to a valid signal from one of said third or fourth decoding means for selecting an output of said second mapping means when a complex instruction is decoded or an output of the first mentioned selection means when a simple instruction is decoded.

Claim 11

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture and a second instruction set of said second architecture depending on an architectural context for each said received instruction; a memory management unit determining and providing a page bit indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and providing an architecture qualifying bit indicating said architectural context of a program being read from memory responsive to a processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises a mode control unit which controls the processor state depending on a state of a plurality of bits stored in registers within said processor including an initial stage change bit which determines whether address translation for said second architecture is enabled or disabled, said page bit which indicates whether a current page in memory is for said first or second architectures, and said architecture qualifying bit.

Claim 12

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture and a second instruction set of said second architecture depending on an architectural context for each said received instruction; a memory management unit determining and providing a page bit indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and providing an architecture qualifying bit indicating said architectural context of a program being read from memory responsive to a processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises a mode control unit which controls the processor state depending on a state of a plurality of bits stored in registers within said processor including an initial stage change bit which determines whether address translation for said second architecture is enabled or disabled, said page bit which indicates whether a current page in memory is for said first or second architectures, and said architecture qualifying bit.

Claim 13

The processor recited in claim 8 wherein the processor includes a memory management unit which detects a page mode of instructions read from main memory and informs said mode control unit whether a current page in memory is for said first or second architectures by said second bit.

Claim 14

The processor recited in claim 8 wherein the mode control unit further includes a feature control register and is responsive to a power on or reset condition of the processor to initialize said processor in one of first or second modes corresponding to said first or second architectures, respectively, a state of a bit in said feature control register thereafter enabling dynamic switching between architectural contexts.

Claim 17

The method implemented in a processor recited in claim 11 further comprising the steps of: controlling an interrupt and exception mechanism of the microprocessor; enabling extensions and limitations to the two architectures, said extensions and limitations allowing a single address translation mechanism to translate addresses for a first architecture by mapping onto a translation of a second architecture and a unified interrupt and exception mechanism to handle asynchronous interrupts and page translation and protection related exceptions regardless of an architectural context in effect when an interrupt or exception occurred; and determining an architectural context under which instructions should execute.

Claim 18

A computer system comprising: a microprocessor, said microprocessor supporting two separate and distinct modes of operation corresponding to two separate and distinct instruction-set architectures and running under a single multitasking operating system; an external memory device, said external memory device storing application software for said two architectures; and a system bus connecting said microprocessor to said external memory device; said microprocessor having an internal bus connected to said system bus, said microprocessor including: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction; a memory management unit determining and providing an indication of which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and indicating said architectural context of a program being read from memory as being either code for said first architecture or code for said second architecture responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between said mode of operation corresponding to the first or second architecture and executing one or more decoded instructions according to said architectural context.

Claim 19

A computer system comprising: a microprocessor, said microprocessor supporting two separate and distinct modes of operation corresponding to two separate and distinct instruction-set architectures and running under a single multitasking operating system; an external memory device, said external memory device storing application software for said two architectures; and a system bus connecting said microprocessor to said external memory device; said microprocessor having an internal bus connected to said system bus, said microprocessor including: an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction; a memory management unit determining and providing an indication of which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures; and control means for detecting and indicating said architectural context of a program being read from memory as being either code for said first architecture or code for said second architecture responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between said mode of operation corresponding to the first or second architecture and executing one or more decoded instructions according to said architectural context.

Claim 20

The computer system recited in claim 13 wherein the memory management unit of said microprocessor comprises a mode control mechanism for controlling which of first or second architectural translation methods is to be used by a memory management unit when translating an effective address to a virtual address.

Claim 21

The computer system recited in claim 14 wherein the mode control mechanism controls an instruction fetch and decode mechanism of the processor so that instructions of said first and second architectures fetched and aligned for proper decoding by said instruction decoder.

Claim 22

The computer system recited in claim 15 wherein said memory management unit reads a page mode control bit from a page table entry for said second architecture, said page mode control bit being supplied to said control means to control address translation by said memory management unit.

Claim 23

The computer system recited in claim 13 wherein said control means comprises: an architectural context control mechanism for controlling which architectural context the processor operates under, said architectural context control mechanism controlling an architectural translation method to be used by a memory management unit of the microprocessor when translating an effective address to a virtual address, said architectural context control mechanism further controlling instruction fetch and decode logic of the microprocessor, said architectural context control mechanism further controlling an execution context of process and architected resources, and said architectural context control mechanism further controlling an interrupt and exception mechanism of the microprocessor; and a qualifying mode control mechanism for enabling extensions and limitations to the two architectures, said extensions and limitations allowing a single address translation mechanism to map addresses for one architecture to address translations of another architecture and a unified interrupt and exception mechanism that handles asynchronous interrupts and page translation and protection related exceptions regardless of an architectural context in effect when an interrupt or exception occurs.

Claim 24

The computer system recited in claim 13 wherein said instruction set management means of said microprocessor comprises: first decoding means for decoding instructions for said first instruction set; second decoding means for decoding instructions for said second instruction set; and selection means controlled by said control means for selecting decoded instructions from said first decoding means or decoded instructions from said second decoding means.

Claim 25

The computer system recited in claim 18 wherein said first and second decoding means decode simple instructions of said first and second architectures, simple instructions being instructions that map into a basic operation class and can be handled by a single execution unit, said instruction management means further comprising: third decoding means for decoding complex instructions of said first instruction set; fourth decoding means for decoding complex instructions of said second instruction set; second selection means controlled by said control means for selecting decoded instructions from said third or fourth decoding means; and third selection means responsive to a valid signal from one of said third or fourth decoding means for selecting an output of said third or fourth decoding means when a complex instruction is decoded or an output of the first mentioned selection means when a simple instruction is decoded.

Claim 26

The computer system recited in claim 13 wherein said control means of said microprocessor comprises a mode control unit which controls the processor to be in one of a plurality of states depending on a state of a plurality of bits stored in registers within said processor including a first bit which determines whether address translation for said second architecture is enabled or disabled, a second bit which indicates whether a current page in memory is for said first or second architectures, and a third bit which is an architecture qualifying bit.

Claim 27

The computer system recited in claim 20 wherein the processor includes a memory management unit which detects a page mode of instructions read from main memory and informs said mode control unit whether a current page in memory is for said first or second architectures by said second bit.

Claim 28

The computer system recited in claim 20 wherein the mode control unit further includes a feature control register and is responsive to a power on or reset condition of the processor to initialize said processor in one of first or second modes corresponding to said first and second architectures, respectively, a state of a bit in said feature control register thereafter enabling dynamic switching between architectural contexts.

Claim 29

The computer system recited in claim 13 wherein the microprocessor has a single memory management unit which is implemented using a format common to the two supported architectures.

Claim 30

The computer system recited in claim 13 wherein the microprocessor has a single instruction fetch mechanism shared by the two supported architectures and separate instruction decode mechanisms.

Claim 31

The computer system recited in claim 13 wherein all execution resources of the microprocessor are common to the two supported architectures.

Claim 32

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes corresponding to two separate and distinct modes of operation, said processor comprising: a system interface for connecting to an external memory storing application programs written for said first and second architectures; a memory management unit connected to said system interface, said memory management unit reading a page mode control bit from a page table entry for said second architecture; an instruction unit including a fetch and decode mechanism, said fetch and decode mechanism including first decoding means for decoding instructions for a first instruction set and mapping decoded instructions to one or more decoded instructions for a second instruction set, second decoding means for decoding instructions for a second instruction set, and selection means for selecting decoded instructions decoded by said first or second decoding means; an execution unit connected to receive and execute decoded instructions from said instruction unit, said execution unit having a plurality of registers accessible depending on which of said first or second modes of operation are enabled; and a mode control unit providing an architecture qualifying bit connected to control said instruction unit and said execution unit, said page mode control bit, an initial change bit and said architecture qualifying bit being supplied to said mode control unit and enabling one of said first or second modes of operation to control address translation and controlling said instruction fetch and decode mechanism of the processor so that instructions of said first and second architectures fetched and aligned for proper decoding.

Claim 33

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes corresponding to two separate and distinct modes of operation, said processor comprising: a system interface for connecting to an external memory storing application programs written for said first and second architectures; a memory management unit connected to said system interface, said memory management unit reading a page mode control bit from a page table entry for said second architecture; an instruction unit including a fetch and decode mechanism, said fetch and decode mechanism including first decoding means for decoding instructions for a first instruction set and mapping decoded instructions to one or more decoded instructions for a second instruction set, second decoding means for decoding instructions for a second instruction set, and selection means for selecting decoded instructions decoded by said first or second decoding means; an execution unit connected to receive and execute decoded instructions from said instruction unit, said execution unit having a plurality of registers accessible depending on which of said first or second modes of operation are enabled; and a mode control unit providing an architecture qualifying bit connected to control said instruction unit and said execution unit, said page mode control bit, an initial change bit and said architecture qualifying bit being supplied to said mode control unit and enabling one of said first or second modes of operation to control address translation and controlling said instruction fetch and decode mechanism of the processor so that instructions of said first and second architectures fetched and aligned for proper decoding.

Claim 34

The processor recited in claim 26 wherein said mode control unit controls the processor to be in one of a plurality of states depending on a state of a plurality of bits stored in registers within said processor including a first bit which determines whether address translation for said second architecture is enabled or disabled, a second bit which indicates whether a current page in memory is for said first or second architectures, and a third bit which is an architecture qualifying bit.

Claim 35

The processor recited in claim 27 wherein the mode control unit further includes a feature control register and is responsive to a power on or reset condition of the processor to initialize said processor in one of said first or second modes of operation corresponding to said first and second architectures, respectively, a state of a bit in said feature control register thereafter enabling dynamic switching between architectural contexts.