DRAM cell array with dynamic gain memory cells

Claim 1

A DRAM cell array, comprising: a plurality of dynamic gain memory cells, integrated in a substrate; a selection transistor included in each memory cell formed as a planar MOS transistor, and a memory transistor formed as a vertical MOS transistor; a common source/drain region connecting the selection transistor and the memory transistor to one another; a source/drain region of the memory transistor being connected to a supply voltage line; a source/drain region of the selection transistor being connected to a bit line; a gate electrode of the selection transistor being connected to a word line; a gate electrode of doped silicon in the memory transistor disposed along at least one side of a longitudinal trench; and a silicon structure being doped with the opposite conductivity type of said gate electrode and being disposed in the trench, said silicon structure together with said gate electrode of the memory transistor forming a diode and being connected to said common source/drain region via a contact, and wherein said gate electrode of the memory transistor and said silicon structure are each formed as spacers, which line the sides of said trench.