EP0537203B1
Expired / Lapsed
EP
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Device with self-amplifying dynamic mos transistor storage cells
Assignee: Siemens AG
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Filing: 1991-06-18
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Granted: 1994-09-14
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Expires: 2011-06-18
Abstract
Abstract PCT No. PCT/DE91/00502 Sec. 371 Date Dec. 29, 1992 Sec. 102(e) Date Dec. 29, 1992 PCT Filed Jul. 18, 1991 PCT Pub. No. WO92/01287 PCT Pub. Date Jan. 23, 1992.An arrangement with self-amplifying dynamic MOS transistor storage cells has in each case a MOS selection transistor AT, whose gate is connected to a word line WL, and an MOS storage transistor ST at whose gate a capacitor C for charge storage acts. This self-amplifying storage cell can be written on and read out with only one bit line BL and one word line WL. The two transistors AT and ST are connected in series and a common drain source region DS is connected via a voltage-dependent resistor VR to the gate electrode GST of the control transistor. The advantages reside in the fact that the cell geometry can be scaled without at the same time the quantity Q of charge which can be read out on the bit line BL having to be reduced, in that the quantity Q of charge which can be read out is larger than a charge stored in the capacitor C which acts at the gate of the storage transistor ST and in that the two MOS transistors AT and ST can be produced relatively simply.
Inventors
- 👤 Wolfgang Dr. Krautschneider
- 👤 Lothar Dr. Risch
- 👤 Klaus Lau
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 00:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/404; G11C5/00; G11C5/005; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
255 words
Arrangement with self-amplifying dynamic MOS transistor storage cells, having a multiplicity of MOS transistor storage cells which are electrically conductively connected to only one bit line (BL) in each case, which in each case have one selection transistor (AT) whose gate terminal is electrically conductively connected to a word line (WL), and which have in each case one storage transistor (ST) at whose gate terminal a capacitor acts in order to store information in the form of electrical charge, characterised in that in each case one MOS transistor storage cell is electrically conductively connected to only a single word line (WL), in that both the selection transistor (AT) and the storage transistor (ST) are composed in each case of an MOS transistor, in that a second terminal of the selection transistor (AT) is electrically conductively connected in each case to the bit line (BL), in that in each case the third terminal of the selection transistor (AT) and a second terminal of the storage transistor (ST) form a common drain-source node (DSK), in that in each case the third terminal of the storage transistor (ST) is electrically conductively connected to a supply voltage (V DD ) and in that in each case one voltage-dependent resistor (VR) connects the common drain-source node (DSK) to the gate terminal of the storage transistor (ST) and a capacitor (C), which acts at said terminal, in such a way that a low resistance value occurs during charging and a high resistance value (R) occurs during discharging of the capacitor (C).
Claim 2
Dependent Claim
76 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case the voltage-dependent resistor (VR) is formed by the gate electrode (GST) of the storage transistor (ST) and the common drain-source region (DS) of the two transistors (AT, ST) being composed of semiconductor materials of the same conductance type, the gate electrode (GST) of the storage transistor (ST) having however a higher doping concentration than the drain-source region (DS).
Claim 3
Dependent Claim
122 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case the gate electrode (GST) of the storage transistor (ST) and the common drain-source region (DS) of the two transistors (AT, ST) are composed of semiconductor materials of the same conductance type, the gate electrode (GST) of the storage transistor (ST) having however a higher doping concentration than the common drain-source region (DS), and in that a metallic layer (M) forms together with the gate electrode (GST) of the storage transistor (ST) a Schottky diode which has a lower resistance during the charging of the capacitor (C) which acts at the gate of the storage transistor (ST) than during the discharging of this capacitor (C).
Claim 4
Dependent Claim
125 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case the gate electrode (GST) of the storage transistor (ST) and the common drain-source region (DS) of the two transistors (AT, ST) are composed of highly doped semiconductor materials of the same conductance type, in addition however a highly doped region (G) of a conductance type which is different from the gate electrode (GST) and drain-source region (DS) is inserted between the gate electrode (GST) and the drain-source region (DS) in order to produce a voltage-dependent resistor (VR) which has a lower resistance during the charging of the capacitor (C) which acts at the gate of the storage transistor (ST) than during the discharging of this capacitor (C).
Claim 5
Dependent Claim
32 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case both the selection transistor (AT) and the storage transistor (ST) are of planar construction.
Claim 6
Dependent Claim
54 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case the selection transistor (AT) is of planar construction and the storage transistor (ST) is located in a trench (T), it being possible to feed in the supply voltage (V DD ) directly via a substrate (NSUB).
Claim 7
Dependent Claim
61 words
Arrangement with self-amplifying dynamic MOS transistor storage cells according to Claim 1, characterised in that in each case both the selection transistor (AT) and the storage transistor (ST) are located in the same trench (T), the gate electrode (GST) of the storage transistor (ST) being insulated from a gate electrode (GAT) of the selection transistor (AT) by an intermediate oxide (ZOX).
References Cited (Backward Citations)
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