US5559357A
Expired / Lapsed
US
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Poly LDD self-aligned channel transistors
Assignee: Individual
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Filing: 1995-05-24
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Granted: 1996-09-24
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Expires: 2015-05-24
Abstract
Abstract Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions. The devices also include an insulation spacer that separates the gate electrode from the oxide region between the source and drain contacts and the gate electrode, the insulation spacer preferably made of a nitride. To relieve stress, a thin oxide layer is provided between the insulation spacer and the oxide region. The insulation spacers increase drive currents and move the peak electric field under the spacers, thereby improving device reliability. The insulation spacers also make it possible to define effective channel lengths, thereby avoiding the use of advanced lithography.
Inventors
- 👤 Zoran Krivokapic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:12
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/01346; H10D64/025; H10D64/027; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
260 words
A short channel metal-oxide semiconductor device in a semiconductor substrate separated from neighboring devices wherein trenches are formed in said substrate to define each device, said trenches having sidewalls lined with an oxide liner and filled with an oxide filler, wherein said device includes lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; a gate oxide formed over said gate region; a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal portion and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; and doped polysilicon source and drain contacts, said polysilicon source and drain contacts separated from said horizontal portion of said gate electrode by oxide regions; said short channel metal-oxide semiconductor device fabricated by a method comprising: (a) depositing doped polysilicon layers atop and in contact with said source and drain regions, said polysilicon layers extending beneath said oxide regions and said doped polysilicon source and drain contacts and abutting said oxide liner, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls during subsequent process steps, thereby preventing the formation of parasitic devices in said sidewalls; and (b) depositing vertical insulation spacers to separate said gate electrode from said oxide regions, wherein said method increases the drive currents attainable by said device.
Claim 2
Dependent Claim
260 words
A short channel metal-oxide semiconductor device in a semiconductor substrate separated from neighboring devices wherein trenches are formed in said substrate to define each device, said trenches having sidewalls lined with an oxide liner and filled with an oxide filler, wherein said device includes lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; a gate oxide formed over said gate region; a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal portion and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; and doped polysilicon source and drain contacts, said polysilicon source and drain contacts separated from said horizontal portion of said gate electrode by oxide regions; said short channel metal-oxide semiconductor device fabricated by a method comprising: (a) depositing doped polysilicon layers atop and in contact with said source and drain regions, said polysilicon layers extending beneath said oxide regions and said doped polysilicon source and drain contacts and abutting said oxide liner, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls during subsequent process steps, thereby preventing the formation of parasitic devices in said sidewalls; and (b) depositing vertical insulation spacers to separate said gate electrode from said oxide regions, wherein said method increases the drive currents attainable by said device.
Claim 3
Dependent Claim
235 words
A short channel metal-oxide semiconductor device separated from neighboring devices by a trench whose side-walls are lined with an oxide liner, said trench filled with an oxide filler, said device comprising: (a) lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; (b) a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; (c) a gate oxide formed over said gate region; (d) doped polysilicon layers atop and in contact with each of said source and drain regions; (e) doped polysilicon source and drain contacts atop and in contact with each of said doped polysilicon layers; (f) a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal portion and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; said doped polysilicon source and drain contacts separated from said horizontal portion of said gate electrode by oxide regions; and (g) vertical insulation spacers separating said gate electrode from said oxide regions, wherein said doped polysilicon layers extend beneath said oxide regions and said polysilicon source and drain contacts and abut said oxide liners of said trench sidewalls, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls in subsequent process steps.
Claim 4
Dependent Claim
235 words
A short channel metal-oxide semiconductor device separated from neighboring devices by a trench whose side-walls are lined with an oxide liner, said trench filled with an oxide filler, said device comprising: (a) lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; (b) a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; (c) a gate oxide formed over said gate region; (d) doped polysilicon layers atop and in contact with each of said source and drain regions; (e) doped polysilicon source and drain contacts atop and in contact with each of said doped polysilicon layers; (f) a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal portion and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; said doped polysilicon source and drain contacts separated from said horizontal portion of said gate electrode by oxide regions; and (g) vertical insulation spacers separating said gate electrode from said oxide regions, wherein said doped polysilicon layers extend beneath said oxide regions and said polysilicon source and drain contacts and abut said oxide liners of said trench sidewalls, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls in subsequent process steps.
Claim 5
Dependent Claim
37 words
The device of claim 2 further including a deep implant of the same conductivity as said shallow channel doping region, said deep implant formed beneath said shallow channel doping region and contacting said source and drain regions.
Claim 6
Dependent Claim
13 words
The device of claim 2 wherein said vertical insulation spacers comprise a nitride.
Claim 7
Dependent Claim
20 words
The device of claim 2 wherein said vertical insulation spacers have a thickness ranging from about 300 to 1,000 Å.
Claim 8
Dependent Claim
21 words
The device of claim 2 wherein said vertical insulation spacers are separated from said oxide regions by a thin oxide spacer.
Claim 9
Dependent Claim
39 words
The device of claim 2 wherein the portion of said doped polysilicon layers in contact with said lightly doped source and drain regions is doped to a concentration ranging from about 1×10 18 to 1×10 19 cm -3 .
Claim 10
Dependent Claim
29 words
The device of claim 2 wherein said lightly doped source and drain regions are doped to a concentration ranging from about 1×10 18 to 1×10 19 cm -3 .
Claim 11
Dependent Claim
29 words
The device of claim 2 wherein said heavily doped source and drain regions are doped to a concentration ranging from about 1×10 20 to 1×10 21 cm -3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |