Patent US5850422A successfully refreshed from Google Patents.
US5850422A
Expired / Lapsed
US
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Apparatus and method for recovering a clock signal which is embedded in an incoming data stream
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-07-21
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Granted: 1998-12-15
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Expires: 2015-07-21
Abstract
Abstract A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.
Inventors
- 👤 Dao-Long Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:23
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0996; H03L7/07; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
96 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; retiming the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit immediately after the one of the plurality of clock phases is selected.
Claim 2
Independent Claim
96 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; retiming the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit immediately after the one of the plurality of clock phases is selected.
Claim 3
Independent Claim
137 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; retiming the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit; wherein the operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.
Claim 4
Independent Claim
137 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; retiming the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit; wherein the operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.
Claim 5
Independent Claim
115 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream and a plurality of clock phases to a data sampler circuit; first operating the data sampler circuit to select one of the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode.
Claim 6
Independent Claim
115 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream and a plurality of clock phases to a data sampler circuit; first operating the data sampler circuit to select one of the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode.
Claim 7
Dependent Claim
35 words
The method of claim 3, wherein the first operating step includes the step of: strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase.
Claim 8
Dependent Claim
22 words
The method of claim 3, further including the step of: providing an analog phase-locked loop for generating the plurality of clock phases.
Claim 9
Independent Claim
163 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; first operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode; wherein the first operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.
Claim 10
Independent Claim
163 words
A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of: providing the incoming data stream to a data sampler circuit; first operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; generating a recovered clock signal based on the selected clock phase; second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode; wherein the first operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.
Claim 11
Independent Claim
123 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer; and means for disabling said data sampler circuit while said digital phase-locked loop circuit is operating in a normal data tracking mode.
Claim 12
Independent Claim
123 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer; and means for disabling said data sampler circuit while said digital phase-locked loop circuit is operating in a normal data tracking mode.
Claim 13
Independent Claim
102 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer.
Claim 14
Independent Claim
102 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer.
Claim 15
Dependent Claim
18 words
The apparatus of claim 8, wherein said loop filter circuit includes a bi-directional shift register loop filter circuit.
Claim 16
Dependent Claim
17 words
The apparatus of claim 8, wherein said loop filter circuit includes a up/down counter loop filter circuit.
Claim 17
Independent Claim
131 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer; wherein said data sampler circuit includes a feedback circuit for disabling said data sampler circuit in response to selection of the clock phase indicative of the embedded clock signal.
Claim 18
Independent Claim
131 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising: a data sampler circuit for selecting a clock phase indicative of the embedded clock signal; a clock multiplexer for generating a recovered clock signal based on the selected clock phase; a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer; wherein said data sampler circuit includes a feedback circuit for disabling said data sampler circuit in response to selection of the clock phase indicative of the embedded clock signal.
Claim 19
Independent Claim
109 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for selecting a clock phase from a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and means for disabling said selecting means while said retiming means is operating in the normal data tracking mode, wherein said disabling means includes a feedback circuit which is coupled to said selecting means and said retiming means.
Claim 20
Independent Claim
109 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for selecting a clock phase from a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and means for disabling said selecting means while said retiming means is operating in the normal data tracking mode, wherein said disabling means includes a feedback circuit which is coupled to said selecting means and said retiming means.
Claim 21
Independent Claim
95 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a plurality of clock phases; means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; and means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode, wherein said retiming means includes a lead/lag phase detector circuit coupled to said selecting means.
Claim 22
Independent Claim
95 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a plurality of clock phases; means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; and means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode, wherein said retiming means includes a lead/lag phase detector circuit coupled to said selecting means.
Claim 23
Dependent Claim
25 words
The apparatus of claim 13, wherein said timing means further includes a bi-directional shift register loop filter circuit coupled to said lead/lag phase detector circuit.
Claim 24
Independent Claim
89 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; means for disabling said selecting means while said retiming means is operating in the normal data tracking mode; and a five-stage voltage controlled oscillator for generating the plurality of clock phases, wherein the plurality of clock phases is ten clock phases.
Claim 25
Independent Claim
89 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; means for disabling said selecting means while said retiming means is operating in the normal data tracking mode; and a five-stage voltage controlled oscillator for generating the plurality of clock phases, wherein the plurality of clock phases is ten clock phases.
Claim 26
Independent Claim
97 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a plurality of clock phases; means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and means for disabling said selecting means while said retiming means is operating in the normal data tracking
Claim 27
Independent Claim
97 words
An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising: means for generating a plurality of clock phases; means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal; means for generating a recovered clock signal based on the selected clock phase; means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and means for disabling said selecting means while said retiming means is operating in the normal data tracking
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-14 | 2002-06-15 | 2002-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-14 | 2006-06-15 | 2006-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-14 | 2010-06-15 | 2010-12-15 | $7700.00 | Window Closed / Lapsed |