Method and apparatus for accommodating different issue width implementations of VLIW architectures

Claim 2

A computer system comprising: a bus; a processor having an issue width, the processor coupled to the bus and including, an instruction fetch unit that fetches an issue group of instructions from a memory, and an end of bundle detector that detects if an end of bundle exists within the issue group; and the memory coupled to the bus and having stored therein a plurality of bundles of instructions all instructions in a bundle capable of parallel issue, the bundles of instructions being a size up to a maximum size, the maximum size independent of the issue width of the processor.

Claim 3

The system of claim 1 further comprising: an enabling device coupled to an issue line for enabling the issue line if no end of bundle exists in a preceding instruction of the issue group.

Claim 4

The system of claim 2 wherein the end of bundle detector is a partial decoder.

Claim 5

The system of claim 2 wherein the enabling device changes any instruction within the issue group following an end of bundle to a no op.

Claim 6

The system of claim 2 wherein the enabling device enables by providing a clock signal to the issue line.

Claim 7

The system of claim 2 wherein enabling device is coupled between the instruction fetching device and a full instruction decoder.

Claim 8

The system of claim 1 further comprising: a disabling device coupled to an issue line which disables the issue line if the issue line is after an issue line having an end of bundle in the issue group.

Claim 9

The system of claim 1 wherein the bus is an internal bus and the memory is a cache memory.

Claim 10

The system of claim 1 wherein an end of bundle is indicated by a set bit in an instruction corresponding to the end of bundle, the bit being stored in the memory.

Claim 11

The system of claim 1 wherein a size of bundle is not equal to a size of the issue group.

Claim 12

The system of claim 1 wherein an end of bundle is indicated by a branch instruction stored in the memory.

Claim 13

The system of claim 1 wherein an end of bundle is indicated by one of a branch instruction stored in the memory and an instruction containing a bit set to a predetermined value stored in the memory.

Claim 14

The system of claim 1 wherein each bundle of the plurality of bundles stored in the memory is not a uniform size.

Claim 15

The system of claim 1 wherein no instruction in a bundle is permitted to modify a register accessed by a later occurring instruction in the bundle.

Claim 16

The system of claim 1 wherein the maximum bundle size is greater than the issue width of the processor.

Claim 17

A computer system comprising: a bus; a processor having an issue width, the processor coupled to the bus and including, an instruction fetch unit that fetches an issue group of instructions from a memory, and an end of bundle detector that detects if an end of bundle exists within the issue group; the memory coupled to the bus and having stored therein a plurality of bundles of instructions, the bundles of instructions being a size up to a maximum size, the maximum size independent of the issue width of the processor; and a retirement unit within the processor to insure a later issued instruction can read a valid data from a register modified by an earlier issued instruction of a same bundle, the retirement unit updating the register responsive to a detected end of bundle.

Claim 18

A computer system comprising: a bus; a processor having an issue width, the processor coupled to the bus and including, an instruction fetch unit that fetches an issue group of instructions from a memory, and an end of bundle detector that detects if an end of bundle exists within the issue group; the memory coupled to the bus and having stored therein a plurality of bundles of instructions, the bundles of instructions being a size up to a maximum size, the maximum size independent of the issue width of the processor; and a retirement unit within the processor to insure a later issued instruction can read a valid data from a register modified by an earlier issued instruction of a same bundle, the retirement unit updating the register responsive to a detected end of bundle.