US5459844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Predecode instruction compounding
Assignee: International Business Machines Corp
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Filing: 1994-08-08
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Granted: 1995-10-17
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Expires: 2014-08-08
Abstract
Abstract A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
Inventors
- 👤 Richard J. Eickemeyer
- 👤 Stamatis Vassiliadis
- 👤 Bartholomew Blaner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:47
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3836; G06F9/3853; G06F9/3885
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
227 words
In a digital computer system capable of processing two or more instructions in parallel, a combination, comprising: preparing means for preprocessing a sequence of instructions which may be executed by a plurality of functional units of the digital computer system, each functional unit being capable of processing one or more types of machine-level instructions, said preparing means providing predecode bits to indicate instructions which can be compounded for execution in parallel by one or more of said plurality of functional units of the digital computer system prior to issue for execution of a sequence of instructions to be executed by the plurality of functional units, said preparing means including in combination, (a) means for receiving a group of instructions in said sequence of instructions; (b) an instruction compounding mechanism connected to said means for receiving the group of instructions, said instruction compounding mechanism generating for the group of instructions said predecode bits which denote a grouping of instructions which can be executed in parallel and indicate which instructions of the group of instructions taken from a sequence of existing machine instructions as a sequence of instructions may be compounded and executed in parallel in said digital computer system; and (c) a storage mechanism coupled to the instruction compounding mechanism for receiving and storing the group of instructions and the predecode bits generated for the group of instructions.
Claim 2
Dependent Claim
227 words
In a digital computer system capable of processing two or more instructions in parallel, a combination, comprising: preparing means for preprocessing a sequence of instructions which may be executed by a plurality of functional units of the digital computer system, each functional unit being capable of processing one or more types of machine-level instructions, said preparing means providing predecode bits to indicate instructions which can be compounded for execution in parallel by one or more of said plurality of functional units of the digital computer system prior to issue for execution of a sequence of instructions to be executed by the plurality of functional units, said preparing means including in combination, (a) means for receiving a group of instructions in said sequence of instructions; (b) an instruction compounding mechanism connected to said means for receiving the group of instructions, said instruction compounding mechanism generating for the group of instructions said predecode bits which denote a grouping of instructions which can be executed in parallel and indicate which instructions of the group of instructions taken from a sequence of existing machine instructions as a sequence of instructions may be compounded and executed in parallel in said digital computer system; and (c) a storage mechanism coupled to the instruction compounding mechanism for receiving and storing the group of instructions and the predecode bits generated for the group of instructions.
Claim 3
Dependent Claim
60 words
The combination of claim 1, further including: a plurality of functional instruction processing units which operate in parallel with one another; and an instruction issue mechanism coupled to the storage mechanism for supplying instructions stored therein to different ones of the functional instruction processing units when said predecode bits indicate that said group of instructions may be processed in parallel.
Claim 4
Dependent Claim
38 words
The combination of claim 2, wherein the storage mechanism includes a main memory for storing a block of information including said instructions and a cache storage mechanism connected to the main memory and to the instruction issue mechanism.
Claim 5
Dependent Claim
34 words
The combination of claim 1, further including instruction executing means connected to the storage mechanism for: fetching a plurality of instructions; and in response to predecode bits, executing a plurality of instructions in parallel.
Claim 6
Dependent Claim
17 words
The combination of claim 4, wherein the instruction execution means operates asynchronously with the instruction compounding mechanism.
Claim 7
Dependent Claim
29 words
The combination of claim 1, wherein the storage mechanism includes a main memory having a word size sufficient to append predecode bits to instructions of the group of instructions.
Claim 8
Dependent Claim
30 words
The combination of claim 1, wherein the storage mechanism includes a main memory for storage of the group of instructions and a tag memory for storage of the predecode bits.
Claim 9
Dependent Claim
37 words
The combination of claim 1, wherein the storage mechanism includes a main memory, the main memory including a tag table for the predecode bits and a separate section for storage of a plurality of groups of instructions.
Claim 10
Dependent Claim
41 words
The combination of claim 1, wherein the storage mechanism includes a main memory, the main memory including a page section having a first section for storage of the group of instructions and a second section for storage of the predecode bits.
Claim 11
Dependent Claim
15 words
The combination of claim 1, wherein the group of instructions is a page of instructions.
Claim 12
Dependent Claim
53 words
The combination of claim 1, wherein said predecode bits are associated with the group of instructions based upon data dependencies for indicating whether a subsequent instruction needs to use a result obtained by performance of a preceding instruction and also based upon resource dependencies for indicating whether conflicts exist in use of registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |