Patent US5847990A successfully refreshed from Google Patents.
US5847990A
Expired / Lapsed
US
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Ram cell capable of storing 3 logic states
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-12-23
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Granted: 1998-12-08
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Expires: 2016-12-23
Abstract
Abstract A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.
Inventors
- 👤 V. Swamy Irrinki
- 👤 Ashok Kapoor
- 👤 Raymond T. Leung
- 👤 Alex Owens
- 👤 Thomas R. Wik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
156 words
A memory cell which comprises: an impedance transistor having a first terminal, a second terminal, and a gate, said gate is configured to store a charge indicative of a data magnitude; a flip-flop having an input node, and an output node, wherein said output node is coupled to said first terminal of said impedance transistor, said flip-flop is configured to hold a state indicative of a data sign; a read transistor coupled to said second terminal of said impedance transistor, said read transistor configured to conduct a current through said impedance transistor when a read signal is asserted; a first write transistor coupled to said input node, said first write transistor configured to set the state of said flip-flop when a write signal is asserted; and a second write transistor coupled to said gate of said impedance transistor, said second write transistor configured to store said charge on said gate when said write signal is asserted.
Claim 2
Dependent Claim
156 words
A memory cell which comprises: an impedance transistor having a first terminal, a second terminal, and a gate, said gate is configured to store a charge indicative of a data magnitude; a flip-flop having an input node, and an output node, wherein said output node is coupled to said first terminal of said impedance transistor, said flip-flop is configured to hold a state indicative of a data sign; a read transistor coupled to said second terminal of said impedance transistor, said read transistor configured to conduct a current through said impedance transistor when a read signal is asserted; a first write transistor coupled to said input node, said first write transistor configured to set the state of said flip-flop when a write signal is asserted; and a second write transistor coupled to said gate of said impedance transistor, said second write transistor configured to store said charge on said gate when said write signal is asserted.
Claim 3
Dependent Claim
21 words
The memory cell of claim 1, wherein said flip-flop has a power node coupled to the gate of said impedance transistor.
Claim 4
Dependent Claim
126 words
The memory cell of claim 1, wherein said flip-flop comprises: a power node; a first p-type MOSFET with a first terminal connected to said power node, a second terminal connected to said input node, and a gate connected to said output node; a first n-type MOSFET with a first terminal connected to said input node, a second terminal connected to ground, and a gate connected to said output node; a second p-type MOSFET with a first terminal connected to said power node, a second terminal connected to said output node, and a gate connected to said input node; and a second n-type MOSFET with a first terminal connected to said output node, a second terminal connected to ground, and a gate connected to said input node.
Claim 5
Dependent Claim
41 words
The memory cell of claim 1, wherein said charge being greater than a predetermined value is indicative of a data magnitude of one, and wherein said charge being less than said predetermined value is indicative of a data magnitude of zero.
Claim 6
Dependent Claim
46 words
The memory cell of claim 1 wherein said output node having a voltage greater than a predetermined voltage is indicative of a positive data sign, and wherein the voltage of said output node being less than said predetermined voltage is indicative of a negative data sign.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |