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US5841296A
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Programmable delay element
Assignee: Xilinx Inc
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Filing: 1997-01-21
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Granted: 1998-11-24
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Expires: 2017-01-21
Abstract
Abstract The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate. The slew rate control circuit comprises a plurality of memory cells coupled to a current mirror via a plurality of switches. Appropriate data are programmed or loaded into the memory cells to selectively turn the switches coupled to a current source on or off. The current mirror is also coupled to the inverter or buffer to control its supply current. The slew rate of the inverter or buffer is controlled via the memory cell programming.
Inventors
- 👤 Stephen Churcher
- 👤 Simon A. Longstaff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K5/00; H03K5/13; H03K5/131; H03K5/133; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/00065; H03K2005/00071; H03K2005/0015; H03K2005/00195; H03K2005/00208
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
92 words
An integrated circuit which incorporates a system for post-fabrication equalization of signal delays within the integrated circuit comprising: a logic circuit; a plurality of programmable delay circuits connected to delay signals input to the logic circuit for adjusting the propagation delays of signals inputted to the logic circuit; means for programming the delay circuits after fabrication of the integrated circuit to alter a delay value of each of the programmable delay circuits so that together the delay circuits cause all of the input signal delays to the logic circuit to be equal.
Claim 2
Dependent Claim
92 words
An integrated circuit which incorporates a system for post-fabrication equalization of signal delays within the integrated circuit comprising: a logic circuit; a plurality of programmable delay circuits connected to delay signals input to the logic circuit for adjusting the propagation delays of signals inputted to the logic circuit; means for programming the delay circuits after fabrication of the integrated circuit to alter a delay value of each of the programmable delay circuits so that together the delay circuits cause all of the input signal delays to the logic circuit to be equal.
Claim 3
Dependent Claim
39 words
An integrated circuit which incorporates a system for post-fabrication equalization of signal delays within the integrated circuit according to claim 1, wherein each programmable delay circuit includes an electronically controllable means for altering the propagation delay of electronic signals.
Claim 4
Dependent Claim
90 words
An integrated circuit which incorporates a system for post-fabrication equalization of signal delays within the integrated circuit according to claim 1, wherein each programmable delay circuit includes: a signal path; a delay circuit having a plurality of delay values; a switching circuit connected to the signal path and the delay circuit for switching a selected delay value into the signal path; and a memory programmable after fabrication of the integrated circuit for storage of data which controls the switching circuit and hence the delay value switched into the signal path.
Claim 5
Independent Claim
78 words
A method for post-fabrication equalization of input signal delays within an integrated circuit comprising the steps of: (a) programming a memory in the integrated circuit with a code representative of desired delay times; (b) using the code stored in the memory to control a switch within the integrated circuit to switch into a signal path within the integrated circuit a selected one or more delay elements for equalizing the propagation delays of signals passing into the integrated circuit.
Claim 6
Independent Claim
78 words
A method for post-fabrication equalization of input signal delays within an integrated circuit comprising the steps of: (a) programming a memory in the integrated circuit with a code representative of desired delay times; (b) using the code stored in the memory to control a switch within the integrated circuit to switch into a signal path within the integrated circuit a selected one or more delay elements for equalizing the propagation delays of signals passing into the integrated circuit.
Claim 7
Dependent Claim
91 words
A method for post-fabrication equalization of input signal delays within an integrated circuit according to claim 4, further comprising the steps of: measuring a current value of the propagation delay for a given load; determining whether or not the measured current value of the delay is a desired delay; and reprogramming the memory with a new code to alter the value of the delay if the measured delay is not the desired delay and repeating these steps of delay measurement and delay adjustment until the value of the delay is correct.
Claim 8
Dependent Claim
67 words
A method for post-fabrication equalization of input signal delays within an integrated circuit according to claim 4, wherein steps (a) and (b) are performed for a plurality of memories, switches and delay elements to generate a plurality of delay times for different signals input to a logic circuit of the integrated circuit so that together all signals input to the logic circuit encounter the same delay time.
Claim 9
Dependent Claim
139 words
A field programmable gate array (FPGA) of the type which includes a plurality of external connection pads, a plurality of configurable logic blocks (CLBs), a plurality of input/output blocks (IOBs) connected to each CLB, and a separate connective lead connecting each IOB to a separate pad, wherein the improvement resides in a programmable delay circuit in each IOB which comprises: a signal path through the IOB connected to a corresponding one of the connective leads; a delay circuit having a plurality of delay values; a switching circuit connected to the signal path and the delay circuit for switching a selected delay value into the signal path as it enters the IOB; and a memory programmable after fabrication of the FPGA for storage of data which controls the switching circuit and hence the delay value switched into the signal path.
Claim 10
Dependent Claim
139 words
A field programmable gate array (FPGA) of the type which includes a plurality of external connection pads, a plurality of configurable logic blocks (CLBs), a plurality of input/output blocks (IOBs) connected to each CLB, and a separate connective lead connecting each IOB to a separate pad, wherein the improvement resides in a programmable delay circuit in each IOB which comprises: a signal path through the IOB connected to a corresponding one of the connective leads; a delay circuit having a plurality of delay values; a switching circuit connected to the signal path and the delay circuit for switching a selected delay value into the signal path as it enters the IOB; and a memory programmable after fabrication of the FPGA for storage of data which controls the switching circuit and hence the delay value switched into the signal path.
Claim 11
Dependent Claim
67 words
An FPGA according to claim 7, wherein the connective leads are of different lengths and have different delay values and further wherein for all the IOBs connected to a given CLB, each programmable delay circuit is programmed to have a delay value which, when added to the delay value of the connective lead connected to the IOB containing the programmable delay circuit, is a single predetermined number.
Claim 12
Dependent Claim
34 words
An FPGA according to claim 7, wherein the delay circuit includes a plurality of delay elements, each having a delay value which is a different power of two multiple of a first delay value.
Claim 13
Dependent Claim
16 words
An FPGA according to claim 7, wherein the delay circuit comprises: a plurality of capacitive loads.
Claim 14
Dependent Claim
26 words
An FPGA according to claim 10, wherein the capacitive loads are selected to be different multiples of the power of two of an initial capacitive load.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |