US5831980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shared memory fabric architecture for very high speed ATM switches
Assignee: Intel Corp
•
Filing: 1996-09-13
•
Granted: 1998-11-03
•
Expires: 2016-09-13
Abstract
Abstract A shared memory fabric architecture for asynchronous transfer mode (ATM) switches including a multi-dimensional array of electrically interconnected N*M switch modules, where N>>M. The fabric architecture also includes input ports for providing cells to the array of switch modules. The input ports operate at a predetermined speed S. The fabric architecture additionally includes memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module. The memory devices include on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y<<N.
Inventors
- 👤 Subir Varma
- 👤 Thomas Daniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:07
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/108; H04L49/15; H04L49/1553; H04L49/20; H04L49/201; H04L49/203; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L2012/5638; H04L2012/5646; H04L2012/5651; H04L2012/5678; H04L2012/5679; H04L2012/5681
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
120 words
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M; a plurality of input ports for providing cells to said array of switch modules, said input ports being characterized by a predetermined speed S; and a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each of said switch modules, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y is less than N.
Claim 2
Dependent Claim
120 words
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M; a plurality of input ports for providing cells to said array of switch modules, said input ports being characterized by a predetermined speed S; and a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each of said switch modules, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y is less than N.
Claim 3
Dependent Claim
76 words
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch modules being adapted to support per-VC queuing; a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module; and an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 4
Dependent Claim
76 words
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch modules being adapted to support per-VC queuing; a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module; and an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 5
Dependent Claim
21 words
The shared memory fabric architecture of claim 2 wherein: said multi-dimensional array comprises a two-dimensional array of electrically interconnected switch modules.
Claim 6
Dependent Claim
30 words
The shared memory fabric architecture of claim 2 wherein: said plurality of memory devices comprise a plurality of on-chip, high-speed memory devices and a plurality of off-chip, low-speed memory devices.
Claim 7
Dependent Claim
34 words
The shared memory fabric architecture of claim 4 further comprising: a plurality of input ports for providing cells to said array of switch modules, said input ports being characterized by a predetermined speed S.
Claim 8
Dependent Claim
42 words
The shared memory fabric architecture of claim 5 wherein: the on-chip, high-speed memory devices operate at a high-speed memory speed of N*S; and the off-chip, low-speed memory devices operate at a low-speed memory speed of (Y+M)*S, where Y is less than N.
Claim 9
Dependent Claim
24 words
The shared memory fabric architecture of claim 2 wherein: said plurality of memory devices memory devices of two different speeds at each switch module.
Claim 10
Dependent Claim
84 words
A chip set including a distributed shared memory switch architecture, the chip set including: a plurality of electrically interconnected integrated circuit modules including: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch models being adapted to support per-VC queuing; a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module; and an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 11
Dependent Claim
84 words
A chip set including a distributed shared memory switch architecture, the chip set including: a plurality of electrically interconnected integrated circuit modules including: a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch models being adapted to support per-VC queuing; a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module; and an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 12
Dependent Claim
26 words
The chip set including a distributed shared memory switch architecture of claim 8 wherein: said multi-dimensional array comprises a two-dimensional array of electrically interconnected switch modules.
Claim 13
Dependent Claim
35 words
The chip set including said distributed shared memory switch architecture of claim 8 wherein: said plurality of memory devices comprise a plurality of on-chip, high-speed memory devices and a plurality of off-chip, low-speed memory devices.
Claim 14
Dependent Claim
39 words
The chip set including said distributed shared memory switch architecture of claim 10, further comprising: a plurality of input ports for providing cells to said array of switch modules, said input ports being characterized by a predetermined speed S.
Claim 15
Dependent Claim
43 words
The chip set including said distributed shared memory switch architecture of claim 11 wherein: the on-chip, high-speed memory devices operate at a high-speed memory speed of N*S; and the off-chip, low-speed memory devices operate at a low-speed memory speed of (Y+M)*S, where Y<<N.
Claim 16
Dependent Claim
30 words
The chip set including said distributed shared memory switch architecture of claim 8 wherein: said plurality of memory devices include memory devices of two different speeds at each switch module.
Claim 17
Independent Claim
99 words
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of: (a) providing a plurality of switch modules, said switch modules being adapted to support per-VC queuing; (b) electrically interconnecting the switch modules as a N*M two-dimensional array, where N is greater than M; (c) providing a plurality of memory devices; (d) electrically connecting the memory devices to the array to provide a hierarchical memory structure at each switch module; and (e) providing an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 18
Independent Claim
99 words
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of: (a) providing a plurality of switch modules, said switch modules being adapted to support per-VC queuing; (b) electrically interconnecting the switch modules as a N*M two-dimensional array, where N is greater than M; (c) providing a plurality of memory devices; (d) electrically connecting the memory devices to the array to provide a hierarchical memory structure at each switch module; and (e) providing an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
Claim 19
Independent Claim
130 words
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of: (a) providing a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M; (b) providing a plurality of input ports for providing cells to the array of switch modules, the input ports being characterized by a predetermined speed S; and (c) providing a plurality of memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S where Y is less than N.
Claim 20
Independent Claim
130 words
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of: (a) providing a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M; (b) providing a plurality of input ports for providing cells to the array of switch modules, the input ports being characterized by a predetermined speed S; and (c) providing a plurality of memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S where Y is less than N.
References Cited (Backward Citations)
US4306286A
Cited
US4484292A
Cited
US5222085A
Cited
US4947388A
Cited
US4956839A
Cited
US5214642A
Cited
US5062106A
Cited
US5130977A
Cited
US5140583A
Cited
US5079762A
Cited
US5130975A
Cited
US5173897A
Cited
US5189666A
Cited
US5216669A
Cited
US5136584A
Cited
US5153920A
Cited
US5189668A
Cited
US5204857A
Cited
US5166926A
Cited
US5130984A
Cited
US5220563A
Cited
US5229991A
Cited
US5247516A
Cited
US5274768A
Cited
US5329623A
Cited
US5412655A
Cited
US5440523A
Cited
US5557610A
Cited
US5557611A
Cited
US5548587A
Cited
US5533020A
Cited
US5517495A
Cited
US5548588A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |