Patent US5831313A successfully refreshed from Google Patents.
US5831313A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Structure for improving latch-up immunity and interwell isolation in a semiconductor device
Assignee: Renesas Electronics America Inc
•
Filing: 1996-08-15
•
Granted: 1998-11-03
•
Expires: 2016-08-15
Abstract
Abstract A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.
Inventors
- 👤 Chung-Chyung Han
- 👤 Jeong Yeol Choi
- 👤 Cheun-Der Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:10
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
116 words
A semiconductor device comprising: a substrate having an upper surface; a first semiconductor region extending into said substrate from said upper surface, said first semiconductor region having a lower boundary located below said upper surface and a side boundary extending from said upper surface to said lower boundary; a second semiconductor region continuous with said first semiconductor region along to said side boundary; and a third semiconductor region continuous with said first semiconductor region along said lower boundary, wherein said third semiconductor region is continuous with said side boundary, wherein said first, second and third semiconductor regions have a first conductivity type, and wherein said second and third semiconductor regions have a substantially uniform dopant concentration.
Claim 2
Dependent Claim
116 words
A semiconductor device comprising: a substrate having an upper surface; a first semiconductor region extending into said substrate from said upper surface, said first semiconductor region having a lower boundary located below said upper surface and a side boundary extending from said upper surface to said lower boundary; a second semiconductor region continuous with said first semiconductor region along to said side boundary; and a third semiconductor region continuous with said first semiconductor region along said lower boundary, wherein said third semiconductor region is continuous with said side boundary, wherein said first, second and third semiconductor regions have a first conductivity type, and wherein said second and third semiconductor regions have a substantially uniform dopant concentration.
Claim 3
Dependent Claim
18 words
The semiconductor device of claim 1 wherein said second semiconductor region is continuous with said third semiconductor region.
Claim 4
Dependent Claim
33 words
The semiconductor device of claim 1 wherein said substantially uniform dopant concentration of said second semiconductor region and said third semiconductor region is greater than a dopant concentration of said first semiconductor region.
Claim 5
Dependent Claim
115 words
The semiconductor device of claim 1 further comprising: a fourth semiconductor region extending into said substrate from said upper surface, said fourth semiconductor region having a lower boundary located below said upper surface and a side boundary extending from said upper surface to said lower boundary of said fourth semiconductor region adjacent said side boundary of said first semiconductor region; a fifth semiconductor region continuous with said fourth semiconductor region along said side boundary of said fourth semiconductor region; and a sixth semiconductor region continuous with said fourth semiconductor region along said lower boundary of said fourth semiconductor region, wherein said sixth semiconductor region is continuous with said side boundary of said fourth semiconductor region.
Claim 6
Dependent Claim
18 words
The semiconductor device of claim 4 wherein said fifth semiconductor region is continuous with said sixth semiconductor region.
Claim 7
Dependent Claim
20 words
The semiconductor device of claim 4 wherein said fifth semiconductor region and said sixth semiconductor region have uniform dopant concentrations.
Claim 8
Dependent Claim
29 words
The semiconductor device of claim 6 wherein said fifth semiconductor region and said sixth semiconductor region have dopant concentrations greater than a dopant concentration of said fourth semiconductor region.
Claim 9
Dependent Claim
25 words
The semiconductor device of claim 4 wherein said fourth, fifth and sixth semiconductor regions are of a second conductivity type opposite said first conductivity type.
Claim 10
Dependent Claim
26 words
The semiconductor device of claim 4 wherein said second, third, fifth and sixth semiconductor regions are regions with low resistivity which inhibit vertical and lateral latch-up.
Claim 11
Dependent Claim
44 words
The semiconductor device of claim 1 further comprising: a source region located at said upper surface in said first semiconductor region; a drain region located at said upper surface in said first semiconductor region; and a gate structure located over said first semiconductor region.
Claim 12
Dependent Claim
16 words
The semiconductor device of claim 1 wherein said first semiconductor region is a first well region.
Claim 13
Dependent Claim
28 words
The semiconductor device of claim 11 wherein said third semiconductor region is continuous with a seventh semiconductor region having a second conductivity type opposite said first conductivity type.
Claim 14
Dependent Claim
19 words
The semiconductor device of claim 12 wherein said seventh semiconductor region is the main body of said semiconductor substrate.
Claim 15
Dependent Claim
41 words
The semiconductor device of claim 1 further comprising a mask over said upper surface of said substrate, said mask having a first portion overlying a portion of said first semiconductor region, said first portion of said mask having a sloped surface.
Claim 16
Dependent Claim
23 words
The semiconductor device of claim 14 wherein a profile of said second semiconductor region is similar to a profile of said sloped surface.
Claim 17
Dependent Claim
68 words
The semiconductor device of claim 1 further comprising a mask over said upper surface of said substrate, said mask having a first portion and a second portion, said first portion of said mask overlying a portion of said first semiconductor region, wherein said first portion of said mask comprises a first layer and wherein said second portion of said mask comprises said first layer and a second layer.
Claim 18
Dependent Claim
14 words
The semiconductor device of claim 16 wherein said first layer overlies said second layer.
References Cited (Backward Citations)
US4710477A
Cited
US4947227A
Cited
US5247200A
Cited
US4975764A
Cited
US5408125A
Cited
US5362981A
Cited
US5501993A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |