US4947227A
Expired / Lapsed
US
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Latch-up resistant CMOS structure
Assignee: Texas Instruments Inc
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Filing: 1985-09-16
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Granted: 1990-08-07
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Expires: 2005-09-16
Abstract
Abstract A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.
Inventors
- 👤 Clarence W. Teng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
94 words
A CMOS structure having improved latch-up immunity, comprising: a substrate having a crystalline surface portion on which MOS devices are formed; a well of polycrystalline semiconductor material disposed within said substrate and having an upper surface approximately coplanar with the surface of said substrate, said well having tapered sidewalls; a layer of isolating material entirely separating said semiconductor material from said substrate; an MOS transistor of a first conductivity type formed in said well of semiconductor material; and an MOS transistor of a second conductivity type formed in said surface portion of said substrate.
Claim 2
Dependent Claim
94 words
A CMOS structure having improved latch-up immunity, comprising: a substrate having a crystalline surface portion on which MOS devices are formed; a well of polycrystalline semiconductor material disposed within said substrate and having an upper surface approximately coplanar with the surface of said substrate, said well having tapered sidewalls; a layer of isolating material entirely separating said semiconductor material from said substrate; an MOS transistor of a first conductivity type formed in said well of semiconductor material; and an MOS transistor of a second conductivity type formed in said surface portion of said substrate.
Claim 3
Dependent Claim
42 words
The MOS structure of claim 1, wherein said substrate includes a plurality of said wells of said polycrystalline semiconductor material, and wherein said polycrystalline semiconductor material of each well of said plurality of wells includes transistors only of said first conductivity type.
Claim 4
Dependent Claim
17 words
The CMOS structure of claim 1 wherein said first type of MOS transistor comprises a PMOS transistor.
Claim 5
Dependent Claim
19 words
The structure of claim 1, wherein said semiconductor material is entirely separated from said substrate by full oxide isolation.
Claim 6
Dependent Claim
14 words
The structure of claim 1, wherein said isolating material consists essentially of silicon dioxide.
Claim 7
Dependent Claim
23 words
The structure of claim 1, wherein said surface portion of said substrate comprises channel stops in proximity to said sidewalls of said well.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |