Patent US5828579A successfully refreshed from Google Patents.
US5828579A
Expired / Lapsed
US
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Scan segment processing within hierarchical scan architecture for design for test applications
Assignee: Synopsys Inc
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Filing: 1996-08-28
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Granted: 1998-10-27
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Expires: 2016-08-28
Abstract
Abstract A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system environment contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). Individual scan chains are constructed using user defined scan segments and detected inferred segments. Inferred segments are automatically detected if present within IC module designs. When integrated into larger scan chains, the user defined scan segments and the inferred scan segments are not modified during linking. The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define scan configuration information and scan chain specifications (e.g., set scan path commands) to define portions of scan chains. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.
Inventors
- 👤 James Beausang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31704; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318586
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
87 words
In a computer system, a computer implemented method of constructing scan chains within an integrated circuit design, said method comprising the computer implemented steps of: a) accessing a first integrated circuit module design within said integrated circuit design; b) automatically detecting scan resources contained within said first integrated circuit module design, said scan resources detected in step b) referred to as a first inferred scan segment; and c) adding said first inferred scan segment to a first existing scan chain without altering said first inferred scan segment.
Claim 2
Dependent Claim
87 words
In a computer system, a computer implemented method of constructing scan chains within an integrated circuit design, said method comprising the computer implemented steps of: a) accessing a first integrated circuit module design within said integrated circuit design; b) automatically detecting scan resources contained within said first integrated circuit module design, said scan resources detected in step b) referred to as a first inferred scan segment; and c) adding said first inferred scan segment to a first existing scan chain without altering said first inferred scan segment.
Claim 3
Dependent Claim
35 words
A method as described in claim 1 wherein said step b) comprises the step of automatically detecting that said first integrated circuit module design contains scan cells and scan routing resources between said scan cells.
Claim 4
Dependent Claim
33 words
A method as described in claim 1 wherein said step b) comprises the step of detecting annotations within said first integrated circuit module design indicating the presence of said scan resources contained therein.
Claim 5
Dependent Claim
44 words
A method as described in claim 1 wherein said step c) comprises the step of coupling access points associated with said first inferred scan segment with said first existing scan chain, said access points including scan in, scan out, and scan enable signal lines.
Claim 6
Dependent Claim
77 words
A method as described in claim 1 further comprising the steps of: d) identifying a first user defined scan segment, said first user defined scan segment including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and e) adding said first user defined scan segment to said first existing scan chain without altering said first user defined scan segment.
Claim 7
Dependent Claim
162 words
A method as described in claim 5 wherein said first existing scan chain is associated with a first clock domain and further comprising the steps of: accessing a second integrated circuit module design within said integrated circuit design; automatically detecting scan resources contained within said second integrated circuit module design, said scan resources detected referred to as a second inferred scan segment; adding said second inferred scan segment to a second existing scan chain without altering said second inferred scan segment; identifying a second user defined scan segment, said second user defined scan segment including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and adding said second user defined scan segment to said second existing scan chain without altering said user defined scan segment, wherein said second existing scan chain is associated with a second clock domain different from said first clock domain.
Claim 8
Dependent Claim
229 words
In a computer system, a computer implemented method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the computer implemented steps of: a) determining a plurality of inferred scan segments, each inferred scan segment associated with a separate integrated circuit module design within said integrated circuit design; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said step c) comprising the steps of: 1) automatically linking inferred scan segments determined in step a) with user defined scan segments accessed in step b) to form said first scan chain, said inferred scan segments and said user defined scan segments of said first scan chain being of a first common clock domain; 2) automatically linking inferred scan segments accessed in step a) with user defined scan segments accessed in step b) to form said second scan chain, said inferred scan segments and said user defined scan segments of said second scan chain being of a second common clock domain, wherein said first scan chain and said second scan chain are substantially balanced.
Claim 9
Dependent Claim
229 words
In a computer system, a computer implemented method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the computer implemented steps of: a) determining a plurality of inferred scan segments, each inferred scan segment associated with a separate integrated circuit module design within said integrated circuit design; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said step c) comprising the steps of: 1) automatically linking inferred scan segments determined in step a) with user defined scan segments accessed in step b) to form said first scan chain, said inferred scan segments and said user defined scan segments of said first scan chain being of a first common clock domain; 2) automatically linking inferred scan segments accessed in step a) with user defined scan segments accessed in step b) to form said second scan chain, said inferred scan segments and said user defined scan segments of said second scan chain being of a second common clock domain, wherein said first scan chain and said second scan chain are substantially balanced.
Claim 10
Dependent Claim
25 words
A method as described in claim 7 wherein said step c1) and said step c2) do not alter said inferred scan segments during said linkings.
Claim 11
Dependent Claim
22 words
A method as described in claim 7 wherein said step c) is performed pursuant to a user specification set scan path command.
Claim 12
Dependent Claim
54 words
A method as described in claim 7 wherein said first clock domain includes clock signals that trigger on different edges and wherein said steps c1) and c2) individually include the step of adding lock up latches in clock signal paths between scan segments that are clocked with clock signals that trigger on different edges.
Claim 13
Dependent Claim
44 words
A method as described in claim 7 wherein said step a) comprises the step of, for each integrated circuit module design, detecting annotations within said integrated circuit module design indicating the presence of an inferred scan segment of said plurality of inferred scan segments.
Claim 14
Dependent Claim
197 words
In a computer system, a computer implemented method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the computer implemented steps of: a) accessing a user defined scan chain specification; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said first scan chain defined by said user defined scan chain specification, said step c) comprising the steps of: 1) automatically linking a first group of user defined scan segments accessed in step b) and listed in said user defined scan chain specification to form said first scan chain, said first group of user defined scan segments being of a first common clock domain; and 2) automatically linking a second group of user defined scan segments accessed in step b) to form said second scan chain, wherein said first scan chain and said second scan chain are substantially balanced.
Claim 15
Dependent Claim
197 words
In a computer system, a computer implemented method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the computer implemented steps of: a) accessing a user defined scan chain specification; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said first scan chain defined by said user defined scan chain specification, said step c) comprising the steps of: 1) automatically linking a first group of user defined scan segments accessed in step b) and listed in said user defined scan chain specification to form said first scan chain, said first group of user defined scan segments being of a first common clock domain; and 2) automatically linking a second group of user defined scan segments accessed in step b) to form said second scan chain, wherein said first scan chain and said second scan chain are substantially balanced.
Claim 16
Dependent Claim
28 words
A method as described in claim 12 wherein said second group of user defined scan segments of said second scan chain are of said first common clock domain.
Claim 17
Dependent Claim
35 words
A method as described in claim 12 wherein said second group of user defined scan segments of said second scan chain are of a second common clock domain different from said first common clock domain.
Claim 18
Dependent Claim
71 words
A method as described in claim 12 further comprising the step of d) determining a plurality of inferred scan segments, each inferred scan segment associated with a separate integrated circuit module design within said integrated circuit design and wherein said step c 1) comprises the step of automatically linking to said first scan chain inferred scan segments determined in step d) that are listed in said user defined scan chain specification.
Claim 19
Dependent Claim
39 words
A method as described in claim 15 wherein said step c2) comprises the step of automatically linking to said second scan chain certain inferred scan segments determined in step d) that are not linked in said first scan chain.
Claim 20
Dependent Claim
25 words
A method as described in claim 16 wherein said step c1) and said step c2) do not alter said inferred scan segments during said linkings.
Claim 21
Dependent Claim
34 words
A method as described in claim 15 wherein said step d) comprises the step of detecting annotations within said separate integrated circuit module designs indicating the presence of said plurality of inferred scan segments.
Claim 22
Dependent Claim
120 words
In a computer system having a processor and a bus coupled to said processor, a computer readable memory coupled to said bus wherein said computer readable memory containing a set of instructions that when executed causing said computer system to perform a method of constructing scan chains within an integrated circuit design, said method comprising the steps of: a) accessing a first integrated circuit module design within said integrated circuit design; b) automatically detecting scan resources contained within said first integrated circuit module design, said scan resources detected in step b) referred to as a first inferred scan segment; and c) adding said first inferred scan segment to a first existing scan chain without altering said first inferred scan segment.
Claim 23
Dependent Claim
120 words
In a computer system having a processor and a bus coupled to said processor, a computer readable memory coupled to said bus wherein said computer readable memory containing a set of instructions that when executed causing said computer system to perform a method of constructing scan chains within an integrated circuit design, said method comprising the steps of: a) accessing a first integrated circuit module design within said integrated circuit design; b) automatically detecting scan resources contained within said first integrated circuit module design, said scan resources detected in step b) referred to as a first inferred scan segment; and c) adding said first inferred scan segment to a first existing scan chain without altering said first inferred scan segment.
Claim 24
Dependent Claim
37 words
A computer readable memory as described in claim 19 wherein said step b) comprises the step of automatically detecting that said first integrated circuit module design contains scan cells and scan routing resources between said scan cells.
Claim 25
Dependent Claim
35 words
A computer readable memory as described in claim 19 wherein said step b) comprises the step of detecting annotations within said first integrated circuit module design indicating the presence of said scan resources contained therein.
Claim 26
Dependent Claim
46 words
A computer readable memory as described in claim 19 wherein said step c) comprises the step of coupling access points associated with said first inferred scan segment with said first existing scan chain, said access points including scan in, scan out, and scan enable signal lines.
Claim 27
Dependent Claim
79 words
A computer readable memory as described in claim 19 further comprising the steps of: d) identifying a first user defined scan segment, said first user defined scan segment including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and e) adding said first user defined scan segment to said first existing scan chain without altering said first user defined scan segment.
Claim 28
Dependent Claim
164 words
A computer readable memory as described in claim 23 wherein said first existing scan chain is associated with a first clock domain and further comprising the steps of: accessing a second integrated circuit module design within said integrated circuit design; automatically detecting scan resources contained within said second integrated circuit module design, said scan resources detected referred to as a second inferred scan segment; adding said second inferred scan segment to a second existing scan chain without altering said second inferred scan segment; identifying a second user defined scan segment, said second user defined scan segment including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and adding said second user defined scan segment to said second existing scan chain without altering said user defined scan segment, wherein said second existing scan chain is associated with a second clock domain different from said first clock domain.
Claim 29
Dependent Claim
226 words
In a computer system having a processor and a bus coupled to said processor, a computer readable memory coupled to said bus wherein said computer readable memory containing a set of instructions that when executed causing said computer system to perform a method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the steps of: a) accessing a user defined scan chain specification; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said first scan chain defined by said user defined scan chain specification, said step c) comprising the steps of: 1) automatically linking a first group of user defined scan segments accessed in step b) and listed in said user defined scan chain specification to form said first scan chain, said first group user defined scan segments being of a first common clock domain; 2) automatically linking a second group of user defined scan segments accessed in step b) to form said second scan chain, wherein said first and said second scan chain are substantially balanced.
Claim 30
Dependent Claim
226 words
In a computer system having a processor and a bus coupled to said processor, a computer readable memory coupled to said bus wherein said computer readable memory containing a set of instructions that when executed causing said computer system to perform a method of constructing scan chains within a hierarchical structured integrated circuit design, said method comprising the steps of: a) accessing a user defined scan chain specification; b) accessing a plurality of user defined scan segments associated with said integrated circuit design, each of said user defined scan segments including a member list of coupled scan cells and access points to said member list, said access points including scan in, scan out, and scan enable signal lines; and c) automatically constructing a first scan chain and a second scan chain, said first scan chain defined by said user defined scan chain specification, said step c) comprising the steps of: 1) automatically linking a first group of user defined scan segments accessed in step b) and listed in said user defined scan chain specification to form said first scan chain, said first group user defined scan segments being of a first common clock domain; 2) automatically linking a second group of user defined scan segments accessed in step b) to form said second scan chain, wherein said first and said second scan chain are substantially balanced.
Claim 31
Dependent Claim
37 words
A computer readable memory as described in claim 25 wherein said second group of user defined scan segments of said second scan chain are of a second common clock domain different from said first common clock domain.
Claim 32
Dependent Claim
72 words
A computer readable memory as described in claim 25 further comprising the step of d) determining a plurality of inferred scan segments, each inferred scan segment associated with a separate integrated circuit module design within said integrated circuit design and wherein said step c1) comprises the step of automatically linking to said first scan chain inferred scan segments determined in step d) that are listed in said user defined scan chain specification.
Claim 33
Dependent Claim
41 words
A computer readable memory as described in claim 27 wherein said step c2) comprises the step of automatically linking to said second scan chain inferred certain scan segments determined in step d) that are not linked in said first scan chain.
Claim 34
Dependent Claim
27 words
A computer readable memory as described in claim 28 wherein said step c1) and said step c2) do not alter said inferred scan segments during said linkings.
Claim 35
Dependent Claim
36 words
A computer readable memory as described in claim 27 wherein said step d) comprises the step of detecting annotations within said separate integrated circuit module designs indicating the presence of said plurality of inferred scan segments.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |