Automatic test insertion

Claim 1

A method for automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: inputting a synthesized netlist of the logic circuit; generating fault grading logic additions to be added to the synthesized logic circuit using a fault grading tool; modifying the synthesized netlist using outputs of the fault grading tool to incorporate the desired fault grading logic additions in the synthesized logic circuit; performing scan hook-up of the synthesized logic circuit using logic parameters determined by a user; determining buffering associated with scan hook-up and scan mode lines of the synthesized logic circuit; and adding distributed buffering to the netlist of the synthesized logic circuit; whereby the resultant synthesized logic circuit has test insertion logic incorporated therein that includes fault grade percentage and scan capabilities defined by the fault grading logic additions and distributed buffering added to the netlist, respectively.

Claim 2

A method for automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: inputting a synthesized netlist of the logic circuit; generating fault grading logic additions to be added to the synthesized logic circuit using a fault grading tool; modifying the synthesized netlist using outputs of the fault grading tool to incorporate the desired fault grading logic additions in the synthesized logic circuit; performing scan hook-up of the synthesized logic circuit using logic parameters determined by a user; determining buffering associated with scan hook-up and scan mode lines of the synthesized logic circuit; and adding distributed buffering to the netlist of the synthesized logic circuit; whereby the resultant synthesized logic circuit has test insertion logic incorporated therein that includes fault grade percentage and scan capabilities defined by the fault grading logic additions and distributed buffering added to the netlist, respectively.

Claim 7

A method for automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: generating a synthesized netlist corresponding to the logic circuit; reading the synthesized netlist of the logic circuit; providing a fault grading tool; generating fault grading logic additions using the fault grading tool; modifying the synthesized netlist to incorporate the fault grading logic additions therein; adding scan structures to the synthesized netlist; determining buffering associated with scan hook-up and scan mode lines; adding distributed buffering to the synthesized netlist; and outputting a modified netlist of the synthesized logic circuit having test insertion logic added thereto.

Claim 8

A method for automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: generating a synthesized netlist corresponding to the logic circuit; reading the synthesized netlist of the logic circuit; providing a fault grading tool; generating fault grading logic additions using the fault grading tool; modifying the synthesized netlist to incorporate the fault grading logic additions therein; adding scan structures to the synthesized netlist; determining buffering associated with scan hook-up and scan mode lines; adding distributed buffering to the synthesized netlist; and outputting a modified netlist of the synthesized logic circuit having test insertion logic added thereto.

Claim 14

A method of automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: generating a synthesized input netlist corresponding to the logic circuit; reading the synthesized netlist of the logic circuit; entering module definitions, into first database; re-reading the synthesized input netlist; mapping a design hierarchy contained in the synthesized input netlist using module definitions; adding the design hierarchy and design structure data to the first database; providing a fault grading tool; generating fault grading logic additions comprising fault grade percentage logic using the fault grading tool; reading a fault grade recommendation file from the fault grading tool; removing redundant fault grade additions; identifying modules associated with each recommendation file of the fault grading tool; adding nonredundant fault grade additions comprising an observe and control node list into the first database; re-reading the synthesized input netlist; using data stored in the first database, modifying the synthesized netlist to form a resultant output netlist containing the fault grade recommendations provided by the fault grading tool; reading the synthesized output netlist; entering module definitions into a second database; re-reading the output netlist; mapping scan chains into the design hierarchy stored in the second database; determining how many scan chains are required for each module of the logic circuit and associated module interconnections; determining required mode line buffering; re-reading the synthesized input netlist; using the data stored in the second database, inserting required scan structures and distributed buffering into the logic and adding clock ports into modules that require them to form a resultant output netlist; and generating a control file for the fault grading tool that describes the scan structures in the output netlist, wherein the control file is used by the fault grading tool to verify fault grade percentage and verify scan structure topology and correctness.

Claim 15

A method of automatically inserting test logic into a synthesized logic circuit, said method comprising the steps of: generating a synthesized input netlist corresponding to the logic circuit; reading the synthesized netlist of the logic circuit; entering module definitions, into first database; re-reading the synthesized input netlist; mapping a design hierarchy contained in the synthesized input netlist using module definitions; adding the design hierarchy and design structure data to the first database; providing a fault grading tool; generating fault grading logic additions comprising fault grade percentage logic using the fault grading tool; reading a fault grade recommendation file from the fault grading tool; removing redundant fault grade additions; identifying modules associated with each recommendation file of the fault grading tool; adding nonredundant fault grade additions comprising an observe and control node list into the first database; re-reading the synthesized input netlist; using data stored in the first database, modifying the synthesized netlist to form a resultant output netlist containing the fault grade recommendations provided by the fault grading tool; reading the synthesized output netlist; entering module definitions into a second database; re-reading the output netlist; mapping scan chains into the design hierarchy stored in the second database; determining how many scan chains are required for each module of the logic circuit and associated module interconnections; determining required mode line buffering; re-reading the synthesized input netlist; using the data stored in the second database, inserting required scan structures and distributed buffering into the logic and adding clock ports into modules that require them to form a resultant output netlist; and generating a control file for the fault grading tool that describes the scan structures in the output netlist, wherein the control file is used by the fault grading tool to verify fault grade percentage and verify scan structure topology and correctness.