Semiconductor memory device including an SOI substrate

Claim 2

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, and a body region located between said source region and said drain region, wherein the body region of each of said plurality of second N channel MOS semiconductor elements is constantly electrically fixed to increase the source/drain breakdown voltage of said each of said plurality of second N channel MOS semiconductor elements and the body region of at least one of said plurality of P channel MOS semiconductor elements is continuously electrically floating.

Claim 3

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, and a body region located between said source region and said drain region, wherein the body region of each of the plurality of first and second N channel MOS semiconductor elements is (constantly electrically fixed to increase the source/drain breakdown voltage of said each of the plurality of first and second N channel MOS semiconductor elements, and the body region of each of said plurality of P channel MOS semiconductor elements is continuously electrically floating.

Claim 4

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, and a body region located between said source region and said drain region, wherein the body region of each of the plurality of first and second N channel MOS semiconductor elements is (constantly electrically fixed to increase the source/drain breakdown voltage of said each of the plurality of first and second N channel MOS semiconductor elements, and the body region of each of said plurality of P channel MOS semiconductor elements is continuously electrically floating.

Claim 5

The semiconductor memory device according to claim 1, wherein said each of said plurality of second N channel MOS semiconductor elements comprises an N channel MOS transistor.

Claim 6

The semiconductor memory device according to claim 1, wherein said each of said plurality of second N channel MOS semiconductor elements comprises an N channel MOS capacitor.

Claim 7

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, and a body region located between said source region and said drain region, wherein the body region of at least one of said plurality of second N channel MOS semiconductor elements is constantly supplied with a first predetermined potential and the body region of each of the others of said plurality of second N channel MOS semiconductor elements is supplied with a second predetermined potential different from the first predetermined potential to increase the source/drain breakdown voltage of said each of said plurality of second N channel MOS semiconductor elements, and the body region of at least one of said plurality of P channel MOS semiconductor elements is constantly electrically floating.

Claim 8

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, and a body region located between said source region and said drain region, wherein the body region of at least one of said plurality of second N channel MOS semiconductor elements is constantly supplied with a first predetermined potential and the body region of each of the others of said plurality of second N channel MOS semiconductor elements is supplied with a second predetermined potential different from the first predetermined potential to increase the source/drain breakdown voltage of said each of said plurality of second N channel MOS semiconductor elements, and the body region of at least one of said plurality of P channel MOS semiconductor elements is constantly electrically floating.

Claim 9

The semiconductor memory device according to claim 5, wherein said first predetermined potential is constant.

Claim 10

The semiconductor memory device according to claim 5, wherein said first predetermined potential is variable.

Claim 11

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, a body region located between said source region and said drain region, an insulation film formed on said body region, and a gate electrode formed on said insulation film, wherein the body region of at least one of said plurality of second N channel MOS semiconductor elements extends longer than the gate electrode of said at least one of said plurality of second N channel MOS semiconductor elements and is constantly electrically fixed to increase the source/drain breakdown voltage of said at least one of said plurality of second N channel MOS semiconductor elements, and the body region of at least one of said plurality of P channel MOS semiconductor elements is continuously electrically floating.

Claim 12

A semiconductor memory device comprising a plurality of first N channel MOS semiconductor elements receiving a power supply potential, a plurality of second N channel MOS semiconductor elements receiving a boosted potential higher than the power supply potential, and a plurality of P channel MOS semiconductor elements, wherein said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements are formed on an SOI substrate, each of said plurality of first and second N channel MOS semiconductor elements and said plurality of P channel MOS semiconductor elements including a source region, a drain region, a body region located between said source region and said drain region, an insulation film formed on said body region, and a gate electrode formed on said insulation film, wherein the body region of at least one of said plurality of second N channel MOS semiconductor elements extends longer than the gate electrode of said at least one of said plurality of second N channel MOS semiconductor elements and is constantly electrically fixed to increase the source/drain breakdown voltage of said at least one of said plurality of second N channel MOS semiconductor elements, and the body region of at least one of said plurality of P channel MOS semiconductor elements is continuously electrically floating.

Claim 13

The semiconductor memory device according to claim 8, wherein the body region of each of said plurality of P channel MOS semiconductor elements is constantly electrically floating.