Charge pump circuit having different threshold biases of the transistors

Claim 2

A charge pump circuit comprising: an input diode element having an input terminal constituted by connecting a gate of a transistor to one end of a current path of said transistor, and an output terminal constituted by the other end of said current path; and a plurality of boosting unit circuits connected to each other, wherein each boosting unit circuit: consists exclusively of a single transistor connected in a diode configuration and a single capacitance element, has an input terminal constituted by directly connecting a gate of the single transistor to one end of a current path of the single transistor, and has the capacitance element connected at one end to said input terminal; said input terminal of said input diode element being connected to a first power source; said input diode element being connected to a first of said plurality of boosting unit circuits; said plurality of boosting unit circuits being connected such that the diode configurations have a same polarity; the other ends of the capacitance elements of adjacent ones of said plurality of boosting unit circuits respectively receiving clock signals opposite in polarity to each other; said charge pump circuit using a potential supplied by said first power source, sequentially boosting a charge stored in one of said plurality of boosting unit circuits by sequentially transferring said charge to subsequent ones of said plurality of boosting unit circuits in response to said clock signals, and outputting an output voltage at an output terminal of a last one of said plurality of boosting unit circuits; wherein said single transistors of, among said plurality of boosting unit circuits, an "m (positive integer)" and an "m+1" boosting unit circuits, as counted from said input diode element, receive a first substrate potential, while said single transistor of an "m+2" boosting unit circuit receives a second substrate potential different from said first substrate potential.

Claim 3

A circuit as claimed in claim 1, wherein said transistors comprise n-MOSFETs, and wherein said second substrate potential is higher than said first substrate potential.

Claim 4

A circuit as claimed in claim 2, wherein said first power source comprises a power source having a potential higher than a ground potential.

Claim 5

A circuit as claimed in claim 1, wherein said transistors comprise p-MOSFETs, and wherein said second substrate potential is lower than said first substrate potential.

Claim 6

A circuit as claimed in claim 1, wherein said said first power source comprises a power source having a ground potential.

Claim 7

A charge pump circuit comprising: an input diode element having an input constituted by connecting a gate of a transistor to one end of a current path thereof, and an output terminal constituted by the other end of said current path; and a plurality of boosting unit circuits connected to each other, wherein each boosting unit circuit comprises: a transistor connected in a diode configuration and a capacitance element, has an input terminal constituted by connecting a gate of the transistor to one end of a current path of the transistor, and has the capacitance element connected at one end to said input terminal; said input terminal of said input diode element being connected to a first power source; said input diode element being connected to a first of said plurality of boosting unit circuits; said plurality of boosting unit circuits being connected such that the diode configurations have a same polarity; the other ends of the capacitance elements of adjacent ones of said plurality of boosting unit circuits respectively receiving clock signals opposite in polarity to each other; said charge pump circuit using a potential supplied by said first power source, sequentially boosting a charge stored in one of said plurality of boosting unit circuits by sequentially transferring said charge to subsequent ones of said plurality of boosting unit circuits in response to said clock signals, and outputting an output voltage at an output terminal of last one of said plurality of boosting unit circuits; wherein said transistors of, among said plurality of boosting unit circuits, an "m (positive integer)" and an "m+1" boosting unit circuits, as counted from said input diode element, have a first substrate potential, while said transistor of an "m+2" boosting unit circuit has a second substrate potential different from said first substrate potential; and further comprising a level detecting circuit for detecting a level of the output voltage, wherein said second substrate potential is controlled by an output of said level detecting circuit.

Claim 8

A charge pump circuit comprising: an input diode element having an input constituted by connecting a gate of a transistor to one end of a current path thereof, and an output terminal constituted by the other end of said current path; and a plurality of boosting unit circuits connected to each other, wherein each boosting unit circuit comprises: a transistor connected in a diode configuration and a capacitance element, has an input terminal constituted by connecting a gate of the transistor to one end of a current path of the transistor, and has the capacitance element connected at one end to said input terminal; said input terminal of said input diode element being connected to a first power source; said input diode element being connected to a first of said plurality of boosting unit circuits; said plurality of boosting unit circuits being connected such that the diode configurations have a same polarity; the other ends of the capacitance elements of adjacent ones of said plurality of boosting unit circuits respectively receiving clock signals opposite in polarity to each other; said charge pump circuit using a potential supplied by said first power source, sequentially boosting a charge stored in one of said plurality of boosting unit circuits by sequentially transferring said charge to subsequent ones of said plurality of boosting unit circuits in response to said clock signals, and outputting an output voltage at an output terminal of last one of said plurality of boosting unit circuits; wherein said transistors of, among said plurality of boosting unit circuits, an "m (positive integer)" and an "m+1" boosting unit circuits, as counted from said input diode element, have a first substrate potential, while said transistor of an "m+2" boosting unit circuit has a second substrate potential different from said first substrate potential; and further comprising a level detecting circuit for detecting a level of the output voltage, wherein said second substrate potential is controlled by an output of said level detecting circuit.

Claim 9

A circuit as claimed in claim 1, wherein one of said first and second substrate potentials is Vcc and the other is ground.

Claim 10

A circuit as claimed in claim 2, wherein the circuit is formed on a p-type substrate, and wherein said n-MOSFET transistor of said m+2 boosting circuit is formed in a p-well that is surrounded by an n-well, and wherein said second substrate potential is applied to both p-well and n-well.

Claim 11

A circuit as claimed in claim 2, wherein said second substrate potential is Vcc.